FW: Verilog-AMS LRM Committee Meeting

Hi all,

I sent this note last week but it looks like it didnt reach people
(actually i didnt get my own copy). My apologies for the same.

Regards,
Sri

-----Original Message-----
From: Chandrasekaran Srikanth-A12788
To: 'verilog-ams@eda.org'
Sent: 7/2/04 9:40 PM
Subject: RE: Verilog-AMS LRM Committee Meeting

  
Hi all,

Just to confirm the next Verilog-AMS committee call will be on the 11th
of July, 4:30pm, PT. The dialin info is the same as before (thanks to
cadence).

Regards,
Sri

>>-----Original Message-----
>>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>>Behalf Of Chandrasekaran Srikanth-A12788
>>Sent: Tuesday, June 29, 2004 7:27 AM
>>To: 'verilog-ams@eda.org'
>>Subject: Verilog-AMS LRM Committee Meeting
>>
>>Hi all,
>>
>>I apologize for some confusion regarding the schedule of the
verilog-ams
>>committee conference calls this month. I have been on travel for most
of
>>the time during this month and also to top that i dont have a
functioning
>>laptop (refused to work last week onwards).
>>
>>I will be back in Australia end of this week - So we can schedule the
next
>>conference call on 5th of July, 4:30pm, Pacific time (I am not sure
>>whether the next monday is a public holiday or not in the US). If
thats
>>the case we will have the call scheduled for 11th of July, same time.
>>
>>I would mainly like to discuss the presentation of Device Modelling to
the
>>Accellera Board during DAC, and also would like to have some
discussion to
>>clarify our plans for LRM2.2 which mainly includes all the device
>>modelling extensions that have been proposed (including m-factor and
>>paramset proposals that are currently being discussed).
>>
>>Sorry for any inconvinience with regards to this.
>>
>>Regards,
>>Sri

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 J.A. Barby  <jabarby@UWaterloo.ca> 
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