Re: proposal to resolve AMS - SystemVerilog logic conflict

Martin,

You raise a good point.

Other names to consider would be logic_AMS, or
logicdiscipline. Personally, I prefer logic_AMS.

Regards,

Alec Stanculescu
>
> Resending this for todays meeting
>
> > -----Original Message-----
> > From: Martin O'Leary
> > Sent: Friday, May 21, 2004 4:37 PM
> > To: verilog-ams@eda.org
> > Subject: proposal to resolve AMS - SystemVerilog logic conflict
> >
> > Here is my proposal to resolve AMS - SystemVerilog contradictory uses of
> > logic declarations
> > Thanks,
> > --Martin
> >
> >
> > Problem:
> > AMS and SystemVerilog both use 'logic' in a contradictory way.
> >
> > This prevents people for mixed AMS and SystemVerilog in the same parse
> > stream.
> >
> > It also is going be a serious roadblock for creating SystemVerilog-AMS.
> >
> > In AMS, logic is discipline defined in the standard discipline header
> > file; disciplines.vams;
> >
> > discipline logic
> > domain discrete;
> > enddiscipline
> >
> > To make declare a net called n as having logic discipline in AMS one does;
> >
> > logic n;
> >
> > SystemVerilog adds another 4-value data type, called logic (see Sections
> > 3.3.2 and 5.6 of the SystemVerilog 3.1a LRM).
> >
> > To create a logic variable called n, one does;
> >
> > logic n;
> >
> > Note logic is almost exactly identical to 'reg' except logic can be
> > declared inside other things (like a struct).
> >
> >
> > Solution:
> >
> > In AMS, the logic discipline defined in disciplines.vams should be removed
> > and replace by a definition for logicdomain.
> > All examples/text in the LRM that use logic should be changed to
> > logicdomain.
> >
> > discipline logicdomain
> > domain discrete;
> > enddiscipline
>
Received on Mon Jul 12 16:54:25 2004