Minutes of AMS, VAMS-CM meetings

AMS Committee meeting, August 9
attendees:
Srikanth Chandrasekaran, Freescale
Geoffrey Coram, Analog Devices
Jon Sanders, Cadence
Shekar Chetput, Cadence
Jim Barby, U Waterloo
Colin McAndrew, Freescale
Kevin Cameron, Altera

We reviewed the changes in draft "g" of the LRM.
Jim pointed out two typos (p138 "to model, to model"
and p218 "thearguments").

The remaining issue is that $table_model does not
seem to be well-enough defined. There are 2 points:

1) For higher-order multi-dimensional tables, there
are additional constraints that must be specified.
(For 1-D table models, there is a paragraph on p.236
describing how to get the extra conditions for 2nd
and 3rd order splines.)
(For linear interpolation in multiple dimensions,
no extra conditions are necessary.)

2) The data probably needs to be on a Cartesian grid.

Jon Sanders promised to get back to Geoffrey no later
than noon Pacific time on Wednesday with a resolution.
The default will be to revise the table model section
to only allow linear interpolation (in 1, 2, or 3
dimensions). A future LRM may include higher-order
interpolation, once all the details are worked out.

The LRM will be sent to the Accellera board on Friday
Then the AMS committee will be on hiatus until September
after the board votes, at which point we will work on
LRM 2.3 to synchronize with 1364-2001.

There was some discussion about the future of AMS.
Presently, it appears that all the work on SystemVerilog
is being done at the IEEE under P1800, and that project
does not allow for new extensions (eg, SV-AMS). Sri
will ask Vassilios about the roadmap for AMS and
Accellera's commitment to SV-AMS.

Those of you at companies with board representation
at Accellera should contact your representatives and
ask them to get the board to commit to including AMS
in SV. We need a commitment from the SV side to
include our work in the SV LRM; presently, AMS has
to keep chasing the digital Verilog standard
(1364-2001 and -2005, SV) and we have to keep working
to make sure we're not in conflict.

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VAMS-CM subcommittee meeting, August 10
attendees:
Srikanth Chandrasekaran, Freescale
Geoffrey Coram, Analog Devices
Jim Barby, U Waterloo
Colin McAndrew, Freescale
Laurent Lemaitre, Freescale
Marek Mierzwinski, Tiburon

No one had any further comments; the LRM draft "g"
is fine except for the table model details mentioned
in the AMS meeting.

Colin noted that ADMS and probably other Verilog-A
compilers will continue to use attributes to tag
instance and model parameters to fit the Spice
netlist format; it will be a while before netlisters
generate Verilog-style netlists with paramsets.

If there are any other typos found in draft "g"
please be sure to submit them ASAP. I will be
sending the LRM to Sri on Thursday afternoon
(Eastern time -- probably around noon Pacific).
Sri asked for the frame source and two PDF
versions, one with and one without change bars.
The version will be "2.2" (no draft letter) and
the date will be "September 2004".

Thank you all for your contributions.

-- 
Geoffrey J. Coram, Ph.D.    Senior CAD Engineer     
Analog Devices, Inc.        Geoffrey.Coram@analog.com 
804 Woburn St., MS-422,     Tel (781) 937-1924
Wilmington, MA 01887        Fax (781) 937-1014