Re: proposal to resolve AMS - SystemVerilog logic conflict (v2.0)

To Kevin's point, let me mention what SV is up to:

http://www.eda.org/sv-bc/hm/2499.html

As written, this proposal doesn't help with "logic" for
two reasons: first, of course, "logic" isn't in 1364,
but also it's not a keyword in Verilog-AMS.

One could add the discipline "pseudo-keywords" to the keyword
list for "VerilogAMS-2.1". I think some implementations do
this; in particular, I had trouble naming a parameter "Acc"
(for the MOS11 model) because Acc is the access function for
nature Acceleration. Personally, I found this overly
restrictive, since it's clear that
  2.0 * Acc
is a reference to the parameter, whereas
  Acc(in)
is the access function.

-Geoffrey

Kevin Cameron wrote:
>
> 'logic' as a new keyword is also a backward compatibility issue for
> non-AMS Verilog. I think the problem should be fixed in SV instead (or
> as well).
> [old proposal for SV fix - http://eda.org/verilog-ams/hm/0697.html].
>
> Either way, I still think it's more important to nail done how we are
> planning to integrate the two dialects, rather than just doing the odd
> patch.
>
> Kev.
>
Received on Tue Nov 30 05:02:28 2004