FW: Regarding SystemVerilog and VerilogAMS

We can discuss this further in the upcoming committee meeting.

Regards,
Sri

-----Original Message-----
From: Srouji, Johny [mailto:johny.srouji@intel.com]
Sent: Wednesday, December 08, 2004 2:30 AM
To: Chandrasekaran Srikanth-A12788
Cc: Sri Chandra; Srouji, Johny
Subject: RE: Regarding SystemVerilog and VerilogAMS

Hi Sri,

In general, I think it is the right direction to align between Verilog AMS and SystemVerilog (this is line w/ P1800 long term goal of alignment w/ Verilog). However, our highest priority at this stage is to complete our first IEEE P1800 standard by September-Oct of 2005.

I shall also raise this topic in the WG F2F meeting on December 15 in order to possibly come up w/ alignment plans.

I will get back to you on this. Thanks,

--- Johny.

-----Original Message-----
From: Chandrasekaran Srikanth-A12788 [mailto:Srikanth.Chandrasekaran@freescale.com]
Sent: Friday, December 03, 2004 3:37 AM
To: Srouji, Johny
Cc: Sri Chandra
Subject: FW: Regarding SystemVerilog and VerilogAMS

Hi,

I was informed that you are chairing the P1800 steering committee. I sent a mail attached below to Mark regarding SystemVerilog and VerilogAMS and going forward merging the two languages together and resolving issues and conflicts as both languages are still evolving and features and constructs are being added.

If you could read through my email below and send me your opinions and thoughts on this matter we can work out a good mechanism to be in a position to merge the two languages and working together moving forward.

Regards,
Sri

-----Original Message-----
From: Chandrasekaran Srikanth-A12788
Sent: Wednesday, December 01, 2004 9:33 AM
To: 'mmaidmen@ichips.intel.com'
Cc: Sri Chandra
Subject: Regarding SystemVerilog and VerilogAMS

Hi,

I am chairman of the VerilogAMS committee under the Accellera organization and I am writing on behalf of that committee to get some clarifications. I was given your contact details by one of the accellera committee members. Accellera has given me the directive to merge the VerilogAMS standards with the SystemVerilog standard (for the digital componenets of mixed signal). Now that SV has been donated to IEEE and has been working under P1800 and VerilogAMS is still under Accellera organization, I am bit unsure on how to liase with the SV committee to work on this issue. Things might have been easier if VerilogAMS was donated to Accellera at the same time and probably put with SV under the same IEEE PAR to work on the merger of the two languages. I have also raised the issue with Accellera but havent got any feedback.

Given that there are lot of enhancements happening on the SV and VerilogAMS standards, I feel its quiet imperative to merge the two standards together sooner than later (keyword conflicts, structural constructs and semantics of the language etc). I also feel its important to establish a communication between SV and VerilogAMS to work on this thread so that we ensure the transition from VerilogAMS to SystemVerilogAMS is smooth. I feel that its important to setup some kind of forum where we could discuss issues facing the designers when the two languages are used together in a design and also initially establish a proposal on the work that needs to be done for merging the two languages.

I feel that this issue has already been delayed by about 6 months to an year. VerilogAMS currently refers to an outdated standard for digital
(IEEE1364-1995) and our current activity is on merging the standard with IEEE164-2001. We feel that it's a step in the correct direction towards merging on the standard with SystemVerilog.

I would like to hear your opinions and thoughts on the same.

Cheers,
Sri

--
Srikanth Chandrasekaran
Freescale Semiconductors, Australia
Ph: +61-8-8168 3592 Fax: 3501