Minutes of VerilogAMS LRM Committee Call - 20/21 Dec 2004

Date: 20 Dec 2004, 1:30pm Pacific Time

Attendees:
CLC Shekar, Cadence
Jim Barby, University of Waterloo
Peter Leibmann, Expedion
Prasanna Tamhankar, Freescale
Graham Helwig, Freescale
Geoffrey Coram, Analog Devices
Kevin Cameron, Altera
Sri Chandra, Freescale

Apologies:
Jon Sanders, Cadence
Marq Kole, Philips
Patrick, Tiburon
Martin O'leary Cadence

Minutes:

The meeting was to mainly discuss agenda, goals & plans for the committee in the upcoming year 2005. Some of the key items that need to be addressed in 2005 by the VerilogAMS committee are:

* AMS integration with SystemVerilog
  - Its quite important that AMS gets integrated into SV as part of the PAR P1800 in IEEE. If there is no strategy for doing this (which is already long overdue) it will be very difficult to integrate the two languages in the future.
  - Sent a note to Johny Srouji from Intel with regards to this integration of SV. The response from Johny didn't sound very positive in terms of SV having this integration high in their agenda. It was planned to be discussed at the SV committee meeting on 15th of December. Kevin participated in the meeting and updated that there was no discussions on this issue.
  - There is a strong feeling that the push for this within SV might have to come probably more from design houses rather than vendors for whom this *may not* be a high priority item that needs addressing.
  - The issue of reducing keywords in VerilogAMS is currently being discussed. Changing all the math operators to have a "$" sign in front of it so that they don't need to be identified as keywords in the language. This will be consistent with SystemVerilog which supports external functions and also in line with 136-2005 ($trig functions is not part of 1995 or 2001). This issue will be taken up as part of the LRM 2.3 syntax.

* Merger of the VerilogAMS language with IEEE 1364-2001 syntax
  - Most of the work on updating the syntax to be more consistent with 2001 has already been done earlier this year by Graham.
  - The updated syntax that's currently residing in the eda.org website does not include the LRM2.2 compact modeling extensions. Given that these extensions are pure analog extensions it should be quiet easy to update the syntax. This will be done in the coming weeks and Graham will send out an updated version in January 2005.
  - The updated syntax is more in line & consitent with the syntax description in 2001.
  - There is a stronger need to identify the semantic restrictions of the syntax more clearly and document these in the individual sections to make the different vendor tools behave more consistently and also to be able to write portable models.
  - The review of the entire updated Appendix A might take about 4-5 sessions. Once the syntax is finalized the individual sections will be updated with the new syntax and a more clearer documentation on the semantics.
  - More volunteers might be required to update the individual sections to be able to deliver LRM2.3 in a more timely fashion.

* RF extensions to VerilogAMS
  - The original plan for RF extensions was to start this sub-commitee in 2003/2004; however there have been no volunteers to chair this subcommittee.
  - Critical to address RF extensions as there seems to be a stronger need for the design committee to do behavioural modeling of RF.
  - Geoffrey pointed out to some discussions in designer forurms which predominantly identified supporting complex numbers being the main need for RF; which they might automatically get with SV-AMS (when the languages are merged) since the language supports user defined datatypes.
  - Patrick Leibmann pointed that they currently do lot of hb and envelope transient simulations and the current language does not support the analysis.
  - The subcommittee would also look at the current existing analog operators and be able to extend the behaviour of these operators (that are currently defined specifically for time domain analysis) to frequency domain analysis.
  - The goal of the subcommittee would not only be to indetify new language features that might be required to support RF but extend the behaviour of the currently existing language features.

* Current Proposals being worked upon
  - $table_model proposal: This is currently being worked upon. Patrick has sent addition to the proposal with regards to Isolines. The updated proposal has not yet been sent to the reflector. This will be discussed in the new year.
  - Mixed Signal support for non-transient analysis: Freescale has been working on this proposal to support mixed signal analysis for AC and DC sweep analysis. This has not yet been posted to the reflector.

Regards,
Sri

--
Srikanth Chandrasekaran
Freescale Semiconductors, Australia
Ph: +61-8-8168 3592 Fax: 3501