Minutes of VerilogAMS LRM committee meeting - 17 Jan 2005
Date: 17 Jan
2004, 1:30pm Pacific time
Attendees:
CLC Shekar (Cadence)
Gary Hawisher (Agilent)
Geoffrey Coram (Analog Devices)
Graham Helwig (Freescale)
Jim Barby (University of Waterloo)
Jon Sanders (Cadence)
Kevin Cameron (Altera)
Martin O'leary (Cadence)
Patrick O'Halloran (Tiburon)
Sri Chandra (Freescale)
Apologies:
Marq Kole (Philips)
[Apologies if i had missed a name in this list]
Table model proposal discussions:
* Support for more than one dependent variable:
- Should there be support for more than one dependent variables ie.
multiple output variable support in table model?
- Currently it has to be done using multiple $table_model statements
(one data file for each output data).
- Also, $table_model returns only one value which might have to be
modified. Also this is inconsistent with the rest of the system
task/function defined in chapter 10.
* More control over interpolation algorithm:
- Some users want more control over the interpolation algorithm.
- The current possibility is to write the user's own PLI to handle
the table_model.
- Its not very clear what the user's intention in this request was.
* Scattered data vs data on isolines
- Currently its not clear in the LRM that $table_model is supported
only for Isolines and not for any scattered data. This should be
clarified in the LRM to specify only isolines are supported.
- Some raised concerns about simulator handling scattered data. The
data should be on ordered isolines and probably left to user to
introduce the structure in the input file to the table model.
* Discontinues behaviour in clamp extrapolation
- Discontinuity is introduced in the data when a clamp technique is
used as the slope changes. This will be a problem.
- It was clarified to agilent that LRM2.2 version does not support
clamp technique for the same reason as an extrapolation technique.
* Support for more the 1-D tables:
- Support for more than 1-dimensional table_model request from
Martin. Currently LRM support multi-dimensional table models.
- Not clear whether the interpolation algorithm was being referred or
the dimensions of the table.
* Skipping data & having mutliple outputs:
- Currently there is only one output value: One of the proposals was
interpretting same variable as dependent vs independent in two
different instances based on user specification through extra
arguments??
- It was felt that this would complicate the table_model syntax.
* Supporting Multiple formats for data files:
- There was also a request about supporting multiple formats of input
file for the table model from Martin.
- It was felt that it would be consistent to have one format
specified in the language and not simulator look at input formats.
Conversion scripts could always be written.
- Gary commented that since Spice simulators already support table
models with different formats it might be better for multiple formats
to be supported for convincing users to migrate to VerilogAMS syntax.
* General comments:
- The whole $table_model function seems to be getting very
complicated with the system task specifying input/output values as part
of argument list. Users may not use this in this approach. The
table_model needs extensions to accomodate some of the proposed
enhancements/changes but ensuring ease of usability to the user.
- Probably might need to split the functionality into several
functions. One for building the table model and one for the
interpolating the values for a particular dataset.
- Might want to look at digital table functions and reuse for analog
as appropriate.
- Since both Martin's proposal didnt come before the call and Gary's
comments were not on reflector this will be discussed in the next
fortnightly call.
IEEE-2001 syntax updates:
* Latest updates:
- Graham has updated the updated syntax with the compact model
extensions added on to the BNF work that was done more than a year ago.
- There has been feedback from the Geoffrey on the BNF changes; This
will be addressed before the next call through email before the syntax
is discussed in the committee meeting.
- Due to lack of time, this will be discussed at the next LRM call.
* Review process:
- The current plan is for the committee to review the changebar
additions to the BNF done due to compact modeling updates.
- It will be very time consuming to review the entire document again
since the digital/analog merged BNF was already reviewed.
- Since some of the members were not present in the previous review
of the merge of digital and VerilogA syntax these opinions/feedback can
be posted on the reflector on these sections and discussed.
- Once the BNF is approved the committee might require more
volunteers to update specific individual sections and document
semantics in the chapters more clearly.
* SystemVerilog related discussions
- Would migration to 2001 be done if its going to take as much effort
very soon to again migrate to a SV?
- Tho' users have been requesting this its felt that its not a high
priority items for any of the design/vendor communities to raise the
importance of this work within IEEE.
- Currently the roadmap for SV/AMS integration seems to be very
unclear. SV committee was contacted with regards to this priority, but
it was felt that its not a high priority item for the P1800 committee
to address AMS in 2005.
- It was felt that this might have to be done within the AMS
committee through a DPI based approach (similar to C).
IBIS presentation to VerilogAMS:
* Proposal for IBIS to present to VerilogAMS the latest version of the
standard.
- Since michael wont be available on 31st of January this
presentation will be held on 14th of Febraury.
Next committee call: 31st January 2005, 1:30pm Pacific time.
Same dialin details.
Received on Tue Jan 18 04:44:24 2005
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