Re: analog vs digital domains of variables

Chandrasekaran Srikanth-A12788 wrote:

>Hi all,
>
>I agree that the LRM section 8.2.2 is not clear, but I would say that from BNF/language point of view, any declaration happening inside named scope of either digital or analog blocks should belong to that domain, which means that this should be assigned in the same domain. So in the example below x would be an analog variable and the assignment in the digital block would (should) be illegal. This needs to be added to that section of scoping rules etc.
>
>To deviate a bit further from the particular issue at hand:
>
>In terms of scope, the only confusion (from a language point of view, due to lack/incorrect specification), is when a variable is declared at a module scope and not assinged at all. This variable can be assigned through an inout of an function etc...
>
>This will also happen with the current version of LRM 2.2, where assignments are part of the declaration itself.
>
>Module blackbox;
>  Real x = 10;
>  ...
>Endmodule
>
>In the above case, the assignment is not in either context, and can be accessed in both the context. However, in this regard, I agree with Kevin, in the sense it shouldnt matter whether its analog or digital - the variable just holds a state which can be accessed from either blocks. We need to better clarify these situations also in the LRM, because currently 8.2.2 is bit misleading.
>
>Another aside from a hierarchical usage point of view (in my opinion):
>>From a software/language point of view, I don't think local variables declared in a different scope should be allowed to be assigned outside that scope (using hierarchical identifiers as an lvalue).
>
>Infact hierarchical on the left-hand-side, in my opinion, should not be allowed (however I realize the 1364-2005 allows this).
>
>V(blackbox.a1.br1) <+ 10 (or)
>  blackbox.a1.x = 10;
>  
>
As I said before: this is the kind of thing that gets done in Verilog 
test-benches, so it needs to work for analog (as well as digital) - I 
think it was in the original design objectives for AMS.

Hierarchical design is nice, but real-world circuits are oblivious to 
such things. Parasitics/coupling between instances in a hierarchy may 
not be communicable through their ports and using hierarchical 
references may be the only way to add those items (and they are more 
likely to be necessary for analog than digital).
E.g. if your device model has a temperature variable, you may want to be 
able to control it from a parallel thermal model of  your chip - using 
regular ports to access the temperature doesn't make sense, using 
hierarchical references does.

Kev.

>Cheers,
>Sri
>
>
>-----Original Message-----
>From: Bakalar, Kenneth [mailto:kenneth_bakalar@mentorg.com] 
>Sent: Friday, 18 February 2005 3:40 AM
>To: Geoffrey.Coram; Chandrasekaran Srikanth-A12788; VerilogAMS Reflector
>Subject: RE: analog vs digital domains of variables
>
>
>Sri,
>
>Is it legal to declare a variable in one analog block, and then to assign to it in another analog block in another module (using an hierarchical name)? I hope not, but I don't see where in the LRM it is forbidden.
>
>Ken 
>
>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
>Sent: Thursday, February 17, 2005 11:10 AM
>To: Chandrasekaran Srikanth-A12788; VerilogAMS Reflector
>Subject: analog vs digital domains of variables
>
>Hi, Sri -
>A certain commercial simulator started complaining about variables in my Verilog-A module that were declared but not assigned a value.  The simulator took the view that if the variable is not assigned a value in the analog block (the analog context), then it is a digital variable.
>
>However, in this case, the variable was *declared* in a named block in the analog block.  Is it not clear in this case that the variable belongs in the analog domain? Is it legal to declare a variable in the analog block and then assign a value to it in a digital context? If not, then should section 8.2.2 explictly say the domain is determined by where the variable is declared, or if declared at module scope, by where it is assigned.
>
>module am_i_legal(a);
>  inout a;
>  electrical a;
>  analog begin : the_analog_block
>    real x;
>    V(a) <+ x;
>  end
>
>  initial begin
>    the_analog_block.x=1;
>  end
>endmodule
>
>
>-Geoffrey
>
>
>  
>

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