RE: absdelay and changing td

Oops - didn't see this mail before responding.

But I think the restriction for it to be constant should be moved from the table to actually the BNF.

Cheers,
Sri

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
Sent: Friday, 4 March 2005 1:41 AM
To: Bresticker Shalom-R50386
Cc: VerilogAMS Reflector
Subject: Re: absdelay and changing td


I looked back as far as AMS LRM 2.0 (were you looking at 
Verilog-A 1.0, Shalom?).

I think you are right; that the last sentence was edited
wrong and should have said that changes to *maxdelay* are ignored.

However, in the new LRM, maxdelay is required to be a
constant expression (according to Table 4-23), and thus
the sentence should read
  If maxdelay is specified, it shall be a constant expression.

The example in Figure 4-1 shows the simulation reacting to changes in td.

-Geoffrey


Shalom Bresticker wrote:
> 
> In some old documentation I have, it says,
> 
> "The optional maxdelay argument is both a flag and the maximum allowed 
> delay. If maxdelay is absent, the delay td is held constant at the 
> value from the module's first evaluation. Attempts to change it during 
> an analysis are ignored... If maxdelay is present, then the delay td 
> is allowed to vary between zero and maxdelay."
> 
> So it sounds like an error in the LRM.
> I would speculate an error in editing a change to the text.
> 
> Shalom