RE: `default_transition

From: Tamhankar Prasanna-A14507 <Prasanna.Tamhankar_at_.....>
Date: Thu May 12 2005 - 00:09:39 PDT
Hi Marq,
 
Glad you raised it, I agree, reducing it to a single real number is too harsh, Graham Helwig and I were discussing this issue few days ago to allow things like
 
`default_transition (`SCALE*`TIMESCALE)
 
i.e. allow operators and expressions as long as they can be reduced to a single real number pre-simulation. 
 
Graham will forward you the syntax snippet we were discussing regarding the transition_time.
 
Regards,
Prasanna
------------------------------------------------------
Prasanna Tamhankar
Freescale Semiconductors, Adelaide
+61 8 81683585
------------------------------------------------------ 

-----Original Message-----
From: Marq Kole [mailto:marq.kole@philips.com] 
Sent: Wednesday, 11 May 2005 5:24 PM
To: Tamhankar Prasanna-A14507
Cc: 'verilog-ams@eda.org'
Subject: Re: `default_transition



Prasanna and others, 

I think reducing the constant_expression in this case to a single real number is a bit too harsh. What is needed is the concept of a compiler directive constant expression, that can only contain integers, reals, arithmetic operators, and macros (in a limited form). This would allow such things as: 

        `default_transition 1.2 * `MY_DEFAULT_TRANSITION_TIME

So the syntax would become: 
        default_transition_compiler_directive ::=
                 `default_transition transition_time
       transition_time ::=
                 compiler_directive_constant_expression
       compiler_directive_constant_expression ::=
                 compiler_directive_constant_primary
               | unary_operator compiler_directive_constant_primary
               | compiler_directive_constant_expression binary_operator 
                  compiler_directive_constant_expression
       compiler_directive_constant_primary ::=
                 decimal_number 
                | real_number 
                | compiler_directive_constant_expression_macro
       compiler_directive_constant_expression_macro ::=
                 `define text_macro_name compiler_directive_constant_expression

On the other hand, if the only actual use of the default transition compiler directive is with numbers only, I have no problem with reducing the constant expression to a real number. I do think that it is useful to have access to macros as that would allow more control over this compiler directive, for instance from the command line -- assuming the simulator/compiler supports the definition of macros from the command line (which is not in the standard). 

Regards, 
Marq 


Marq Kole
Competence Leader Analog Simulation, Philips ED&T





	




Tamhankar Prasanna-A14507 <Prasanna.Tamhankar@freescale.com> 


Sent by: 
owner-verilog-ams@eda.org 


03-05-2005 09:48 

        
        To:        "'verilog-ams@eda.org'" <verilog-ams@eda.org> 
        cc:        (bcc: Marq Kole/EHV/RESEARCH/PHILIPS) 
        Subject:        `default_transition 

        Classification:         






Hi all,

Currently, the syntax for `default_transition is 
                default_transition_compiler_directive ::=
                                 `default_transition transition_time
                transition_time ::=
                                 constant_expression

Because `default_transition can *only* be outside a module scope, one cannot have any constant_expression for the transition_time (because constant_expression includes module specific things too, like parameter_identifier) , this should be changed to 

                transition_time ::= 
                                 real_number

Thanks,
Prasanna
------------------------------------------------------
Prasanna Tamhankar
Freescale Semiconductors, Adelaide
+61 8 81683585
------------------------------------------------------ 
Received on Thu May 12 00:09:44 2005

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