Re: Validation suite for Verilog-AMS

I think this is a great goal. It has been discussed in many different language efforts. The challenge has always been to get either enough volunteer time or sufficient funding to make it work. The latter is more successful.

Are you thinking of having Accellera fund one or two people to actually do the work?

An important distinction you can make is feature tests (a different test for each language feature organized along the lines of the LRM) versus functional tests.

Does anyone know of a public Verilog test suite that could be used as a starting point? I am only aware of the VI test suite for VHDL.

Regards
David
--------------------------
David W. Smith
Synopsys Scientist
W: 503.547.6467
M: 650.861.9814

-----Original Message-----
From: owner-verilog-ams@eda.org <owner-verilog-ams@eda.org>
To: verilog-ams@eda.org <verilog-ams@eda.org>
Sent: Thu Jul 21 06:55:22 2005
Subject: Validation suite for Verilog-AMS


Hi, 

Would there by interest in setting up a validation-suite for Verilog-AMS? 

The idea is that a suite of tests for every Verilog-AMS language construct is made that should result in output that is verifyable against a benchmark. A specific subset of this suite should be applicable to the Verilog-A analog language subset. With a simple driver for 

The driver for this idea is any Verilog-A or Verilog-AMS model that is developed on a validated simulator has identical behaviour on any other validated simulator. A reason for Accellera in supporting and driving this would be in increasing the proliferation of Verilog-AMS in as many simulators as possible thereby ensuring this standard language indeed becoming a standard. 

The whole subset can be made largely simulator independent by building up the test suite also from Verilog-A tests, making the suite self-contained and less dependent on the actual ways of integrating Verilog-A in each of the simulators. 

Maybe we can discuss this in one of the upcoming teleconferences - although I've completely lost track of the dates, and I won't be available for the coming three weeks. 

Regards, 
Marq 


Marq Kole
Competence Leader Analog Simulation, Philips ED&T