Is it the intention of the folks donating models to create a standard library that everyone can build netlists against - i.e. vendors can create their own versions of the models if they want (for performance or whatever) but any design only using the standard library models should be portable across all Verilog-AMS simulators, and behave the same in each? Kev. patrick@tiburon-da.com wrote: >Hi Marq, Geoffrey, > > We have a number of the spice models (diode, bjt, mesfet,...) that we are >willing to donate as primitive examples. > >Regards, > >Patrick > >Patrick O'Halloran >Tiburon Design Automation >patrick@tiburon-da.com >707-694-2013 > > > > >>-----Original Message----- >>From: owner-verilog-ams@eda.org >>[mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram >>Sent: Friday, July 22, 2005 8:09 AM >>To: Marq Kole >>Cc: verilog-ams@eda.org >>Subject: Re: SPICE compatibility issues >> >>Marq - >>When you write "Verilog-A versions of all primitives in table E.1" >>does this mean, after the removal of the names diode, bjt, etc.? >>Or have you also written basic models for these devices? >> >>There are a few instances in Verilog LRMs (1364, SV, etc.) of >>code being included, sometimes C code for implementation of >>random functions, or examples. I would certainly support the >>inclusion of the basic primitives as examples, for the >>educational aspect as well as for having V-A versions for >>simulators that don't have a certain primitive. >> >>-Geoffrey >> >> >> >> > > > >Received on Mon Jul 25 13:21:27 2005
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