define and strings

Verilog 1364-1995 and Verilog-AMS 2.1 both had arguments for macros.

String parameters (meaning
  parameter string type="nmos" from {"nmos", "pmos"};
) are new in AMS LRM 2.2, and were modeled after SystemVerilog;
I believe they are not in even the latest 1364-2005 ballot draft.

The "actual arguments" of a macro 1364-1995, AMS 2.1 and 2.2) 
are defined syntactically as "expressions" and thus can include
fixed strings.

-Geoffrey


-- "Muranyi, Arpad" wrote:
> Regarding Verilog-D and the macro definition, again I am new to
> the Verilog world, but I wonder, did Verilog-D have string parameters
> and arguments for `define which could also be string parameters?  If
> not, what will be the verdict?  (It seems that arguments are new to
> `define in LRM v2.2 as well as string parameters, so I suspect that
> Verilog-D may not have them, am I incorrect on that)?