Re: define and strings

To avoid extended discussion of `define etc. I would just like to say 
that declaration of parameters in Verilog-AMS should follow the rules of 
the latest IEEE Verilog or SystemVerilog since this is the common part 
of the MS language. Any differences are a bug/feature that will be fixed 
in a later release in favour of the digital methodology (since that is 
the larger user base).

IMO the Verilog preprocessor is pretty brain-dead and you should use 
something better like cpp if you can which doesn't require the "`". 
There are some Verilog specific freeware preprocessors:

    http://www.verilog.net/free.html

Kev.