RE: VerilogAMS LRM Committee Meeting - 26 July 2005 [not 16th]

I thought the call was at 3:30 (my mistake) - I can call in then if you
guys want to try to have the meeting again.
Thanks,
--Martin

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Muranyi, Arpad
Sent: Tuesday, July 26, 2005 3:22 PM
To: VerilogAMS Reflector
Subject: RE: VerilogAMS LRM Committee Meeting - 26 July 2005 [not 16th]

Sri,

I wonder whether you are talking about pacific daylight savings time,
or regular pacific time?  The two are different by an hour, and
currently
we are in the daylight time.  I just got hung up on after 20 minutes of
waiting, saying that the leader has not arrived...  We have 3:20 p.m.
right now.

Arpad
========================================================================
= 

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Chandrasekaran Srikanth-A12788
Sent: Tuesday, July 26, 2005 3:18 PM
To: Chandrasekaran Srikanth-A12788; 'VerilogAMS Reflector'
Subject: RE: VerilogAMS LRM Committee Meeting - 26 July 2005 [not 16th]

Hi all,

I apologize that we couldn't get through the call today, I hung up after
waiting for about 20 minutes (I hope I got the pacific time correctly).
I am rescheduling the call for next week, August 2nd, 3:00pm Pacific
time with the same agenda. The conference call is sponsored by cadence
and so we needed either Martin O'leary or Jon Sanders to dialin into the
call.

David has given me access to the Mantis database and hopefully I will
populate the spreadsheet items that I wrote into the database.

Regards,
Sri

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Chandrasekaran Srikanth-A12788
Sent: Tuesday, 26 July 2005 1:52 PM
To: 'VerilogAMS Reflector'
Subject: RE: VerilogAMS LRM Committee Meeting - 26 July 2005 [not 16th]



Sorry for the misleading subject line on my meeting agenda email. The
date should read 26th and not 16th.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Chandrasekaran Srikanth-A12788
Sent: Monday, 25 July 2005 6:14 PM
To: 'VerilogAMS Reflector'
Subject: VerilogAMS LRM Committee Meeting - 16 July 2005



Hi all,

After a break of AMS committee meetings, probably its time to re-start
discussions on moving forward with the AMS standards. Also there have
been lot of emails on new topics, work, donations and probably good time
to start the committee meetings.

I have also collated a list of open issues - based on the items that
were sent to me and through the reflector. Hopefully I have covered most
of the issues including the recent issues being discussed - verilog-ams
testsuite, spice compatibility etc. I have not put it in the system that
they use for SV that David Smith suggested (mantis database), since I
havent chased it up with David to get it setup. Hence went back to the
true and trusted excel spreadsheet format.

Agenda:

* How do we move forward - release of AMS versions with minor
enhancements, SV integration, 1364 integration?
* Mixed Signal IC analysis - there has been feedback from Martin on this
* $table_model enhancements - no further updates
* Verilog-AMS validation suite
* Donation of VerilogA versions of spice primivites specified in Table
E.1 from Marq.
* If there is time we can go through the list of open issues - probably
this will be taken up in the next meeting.

With regards to open issues, there are some very simple items that can
be fixed. So we can try to prioritize and see whether there are anybody
who are interested in working on proposals for certain items listed in
the spreadsheet.

Call-In Details:

Time & Date: 26th July, 3pm Pacific Time
Dialin Number & Passcode:
USA Toll Free Number: 877-346-8823
USA Toll Number: +1-203-320-0407 (for international call-in) 
PARTICIPANT PASSCODE: 602538

Regards,
Sri
--
Srikanth Chandrasekaran
Freescale Semiconductor, Inc., Australia
Ph: +61-8-8168 3592 Fax: 3501