Re: hierarchical parameter passing in DC sweep

Marq Kole wrote:
> The fact that the files that contain the output values
> are completely independent of the output syntax of any particular simulator
> makes this approach - or a variation thereof - extremely suitable for
> automated validation.

Definitely true.  My perspective as a V-A compact modeler, though,
finds more use for small-signal verification.  There aren't many
language features in a compact model, and it's unusual to find
problems in the implementation of the basic mathematical operators
that make up the equations for dc and transient.
 
> For the top-level parameters that is true: it appears much less true for
> parameter passing. It was also the first time I tried to pass down a
> parameter from the top-level (Spice) environment to a module instance
> inside Verilog-A. I think it is at least established that this is an issue
> that needs to be addressed in the Verilog-AMS LRM.

I still think this is a simulator issue: if the simulator vendor
relieves the restriction on parameters being constant at run-time,
then the vendor is also responsible for logical extensions such
as passing that varied parameter.

The AMS LRM does need to say more about dc sweeps, though, since we
do expect parameter sweeps, and it would be reasonable to include
a sentence about these parameters being updated in the places they
are passed to.

-Geoffrey