RE: always @(implicit_net)

comments below.


________________________________

	From: owner-verilog-ams@eda.org
[mailto:owner-verilog-ams@eda.org] On Behalf Of Tamhankar
Prasanna-A14507
	Sent: Thursday, August 25, 2005 11:32 PM
	To: 'verilog-ams@eda.org'
	Subject: always @(implicit_net)
	
	

	All,
	
	Have a question about usage of implicit nets in Verilog-AMS, can
implicit nets be used in behavioral blocks ? 

	oleary>

	Yes they can be - as your Verilog-D example shows.

	To take the example;

	 @(implicit_net)

	This is a digital-usage reference of the net "implicit_net'.
There then domain of this net is considered discrete.

	 
	AMS LRM section 3.4.5 says they can be used in structural
descriptions, there are no restrictions on implicit net usage withing
behavior block.
	
	Looks like in a pure digital module (no mixed signal), usage of
always @(implicit_net) is actually allowed.  However, this gets
complicated in a mixed-signal module because the implicit net may either
get resolved to be analog or digital, and doing always
@(analog_implicit_net) is wrong even within a digital block. I have
attached a simple module illustrating the issues below 

	oleary>

	This situation cannot occur because an implicit net is being
used as a digital receiver reference and hence resolved to discrete and
cannot resolve to continuous.

	 
	
	`include "disciplines.vams"
	
	`timescale 1ns/1ns
	//`default_nettype wire
	
	module testImplicitNets;
	
	  reg d;
	  wire dout;
	
	  not #1 (implicitNet1, d);
	  not #1 (implicitNet2 , implicitNet1);
	  not #1 (dout , implicitNet2);
	
	  initial begin
	    #100 d  = 0;
	    #100 d  = 1;
	    #100 d  = 0;
	    #1 $finish;
	  end
	
	  always @( d )              $display( $time, "[DIGITAL]d
toggled to \t",     d );
	  always @( implicitNet1 or implicitNet2 ) $display( $time,
"[DIGITAL]\t\t", implicitNet1, implicitNet2);
	
	  analog begin
	    // @( implicitNet1 or implicitNet2 ) $strobe("[ANALOG]\t\t",
implicitNet1, implicitNet2);
	        @(implicitNet1) $strobe("[ANALOG]implicitNet1 toggled at
time = %g!\n",  $abstime);
	  end
	endmodule
	
	Cheers,
	Prasanna
	------------------------------------------------------
	Prasanna Tamhankar
	Freescale Semiconductors, Adelaide
	+61 8 81683585
	------------------------------------------------------