Re: Notes from my discussion with Johny Srouji (Accellera Technical C hair)

Chandrasekaran Srikanth-A12788 wrote:

>0. Gave outline, membership, current status of AMS committee and the LRM version.
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>1. Interim versions for VerilogAMS: It will be good to have interim VerilogAMS LRM release which synchronizes with 1364-2005 standard before moving to SystemVerilog. SV is still a very high priority and the right direction to move, but given the nature of the task it might be good to first move to 1364-2005 which is a natural step towards p1800. There was a workshop in April set out for discussing plan and also requirements from different members/companies to be involved with, for SV merge and cadence is working on a initial draft proposal - initial plan was to release SV integration early Feb 2006. 
>This is a very difficult task to jump directly to SV from current version of AMS standard. It was agreed to release interim version with 1364-2005 at the same time addressing some of the critical SV incompatibility issues. 
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While I can see the logic in merging with 1364-2005, I'm not convinced 
that EDA vendors are going to be very motivated to work on a Verilog-AMS 
that only has 1364-2005 compatibility when most folks now seem to be 
working on SV. Man-power is somewhat limited, the same people are going 
to be working on the committees at Accellera and IEEE (as far as I can 
tell).

I think 1364-2005 synchronization is only going to delay integration 
with SV, and the committees should make a concerted effort to integrate 
AMS with SV in the next round of SV enhancement.

Both AMS and SV have outstanding issues in the area of back annotation, 
and how the SV/AMS type schemes can be extended to handle more signal 
types. IMO it is extremely important that these issues are addressed 
together, sooner rather than later.

>(Action: Sri) Need to come up with plans/roadmap and release time frames to be sent to Accellera. There might be a board meeting in september and status of AMS also needs to be sent out.
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>2. (Action: Sri) Need to send through documentation/details of the VerilogAMS - latest status report, website links, reflector pages etc
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>3. Release of p1800 - This is planned to happen late Q3 (probably september). Reviews have been completed and its very close to be approved and released. P1800 is a merge of SV and 1364-2005 standards and hence is a superset of the verilog digital standard. The focus of p1800 will be to ensure the smooth transition of verilog users to p1800 system verilog standard. 
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>4. IEEE version with AMS: The plan for the next revision of the p1800 standard would be to release with AMS. This needs to be worked out, planned/detailed and the committee would works towards that as next major milestone. Timeframe? Johny mentioned that the next revision of p1800 may possibly be within 3 years instead of a 5yr wait to integrate into next revision.
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>5. Cooperation between two committees: Once p1800 is released Johny will talk to members on contributing to the merger of p1800 with AMS. He was requesting also the possibility of analog people getting involved in SV/p1800 committee. These needs to be discussed with AMS committee. Will be very difficult to merge p1800 with AMS unless there is involvement within the two groups to come out with common standard. This SV-AMS merger can be done in parallel with the AMS LRM interim version releases.
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It's still my opinion that the AMS committee at Accellera should be 
split, with language development continuing as a subcommittee of the 
P1800 effort and Accellera looking after standard libraries and models.

Since the compatibility issues between AMS and 1364-2005 are probably 
mostly minor I suspect that they could be mostly handled by addenda 
posted on the web, I don't see the requirement for producing full-blown 
LRMs - particularly since the current LRM is a free download.

Kev.

>Regards,
>Sri
>--
>Srikanth Chandrasekaran
>Freescale Semiconductor, Inc., Australia
>Ph: +61-8-8168 3592 Fax: 3501
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