RE: Clarification question

1364-2001 and 1364-2005 do not have parameter arrays. Only
SystemVerilog.

Shalom


>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Chandrasekaran
>Srikanth-A12788
>Sent: Friday, September 09, 2005 3:30 AM
>To: Muranyi, Arpad; verilog-ams@eda.org
>Subject: RE: Clarification question
>
>Hi Arpad,
>
>Okay - that sentence is extremely convoluted and I really don't
understand what it exactly means.
>Infact I tried reading bullet point #2 in the same section "An array
assigned to an instance of a
>module shall be of the exact size of the array bounds of that instance"
in reference to parameter
>arrays. Not exactly clear what this means either.
>
>I am giving a few examples which probably will invoke some discussion
on how it should behave. The
>LRM is not very clear on the semantics of this - probably the above
bullet points are the semantics
>which are difficult to understand :-),
>
>  parameter integer P[0:2] = {0,1};
>            (or)
>  parameter integer P[N:1] = {1,2,3}; // where N is another parameter,
lets say N resolves to 2
>
>I would have expected that both of the above cases would be an error
where the size of the expression
>on the right hand side is not the size defined as part of the range
expression for the parameter. The
>LRM (I think) seems to suggest that the parameter array should be
resized based on the parameter
>assignment expression on the RHS.
>
>Its also possible that vector parameters can be overridden in the child
instantiation line, for
>example:
>
>  child #(.P(Q)) chld1(a,b); // where P & Q are vector parameters of
different sizes. I would have
>thought this will also be an error.
>
>Any other thoughts on what those bullets mean?
>
>Any ideas as to how digital behaves in these cases?
>
>Regards,
>Sri
>
>
>
>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Muranyi, Arpad
>Sent: Friday, 9 September 2005 8:35 AM
>To: verilog-ams@eda.org
>Subject: Clarification question
>
>
>Hello everyone,
>
>Sorry for a few novice questions.
>
>This sentence in the LRM got me.  Could someone please help
>me to understand it (perhaps with some simple examples)?
>This is in section 3.2.4:
>
>"If the array size is changed via a parameter assignment, the parameter
array shall be assigned an
>array of the new size from the same module as the parameter assignment
that changed the parameter
>array size."
>
>First, I would like to understand how the size of an array can be
changed.  Second, I would like to
>understand the second half of the sentence that deals with the
assignment, and module.
>
>Also, is there a way to obtain the size of an array, for example for
the purpose of running a for
>loop as many times as the number of elements in the array?
>
>Seemingly unrelated, question:  Is there a way to read data tables from
files into arrays, kind of
>like the $table_model function does it?  I have seen the $fscan,
$sscan, etc... functions in the
>1364-2001 manual, but are those officially available and supported by
"Verilog-AMS" tools?
>
>
>Thanks,
>
>Arpad
==================================================================