RE: Multi-dimensional arrays?

Thanks to all for the answers regarding my array questions.
 
To be honest with you, one comment got me ticked.  Yes, I
can read, but only what is on the paper.  I can't read the
mind of the vendors, and those who wrote the LRM.  Many of
the responses to this and other questions I have posted to
this forum referred me to the 1364-200x manual.  When I 
look things up in that manual and ask whether it is available
in the Verilog-AMS LRM, or a vendor's implementation of it,
the answer is usually a "no" (remember my $fscan question?).
So how would I know which spec I can go by, when I am trying
to write a "Verilog-AMS" model?
 
It seems that people in this group are forgetting a very
important factor.  Coming from Intel, we have lot of
customers.  They all use different simulation tools.  When
we release models to the customers, we have to make sure
that they can use it, otherwise why bother?  Therefore the
models we write must work on every single tool vendor's
simulator.  The model cannot be based on a specific tool
vendor's interpretation or implementation of what they
think the spec says or includes.  And Intel cannot afford
to write as many versions of the models we are trying to
release as the number of tools on the market.  So the role
of the spec is crucial to provide a common capability and
expectation to all tool vendors and model makers, and for
this reason the spec cannot have bits and pieces laying
around in various documents, such as the Verilog-AMS LRM,
and the 1364-200x manual without spelling out which portions
of these documents are actually making up the "OFFICIAL"
Verilog-AMS language.
 
My $ 0.02...
 
Respectfully,
 
Arpad
===========================================================
 
 
________________________________

From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Sri Chandra
Sent: Tuesday, September 13, 2005 5:32 AM
To: Bresticker, Shalom
Cc: VerilogAMS Reflector
Subject: Re: Multi-dimensional arrays?


Hi,

Just deviating a little bit from the topic of multi-dimensional parameter array - since shalom made a reference to net arrays - With regards to net declarations, AMS also supports multi-dimensional nets - however this is semantically restricted in the analog context...This is mainly supported in AMS to mainly allow the declaration of memories (if somebody is wondering). Syntactically one could do electical [0:3] analogNetA [0:7] - however this is semantically restricted. This syntax is more used in 2-D memory register in the digital context.

regards,
Sri

Bresticker, Shalom wrote: 

	Again, in 1364-200x, variable and net arrays are defined, but not
	parameter arrays.
	
	Shalom
	
	
	  

		-----Original Message-----
		From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
		    

	Behalf Of Geoffrey.Coram
	  

		Sent: Tuesday, September 13, 2005 2:21 PM
		To: Muranyi, Arpad; VerilogAMS Reflector
		Subject: Re: Multi-dimensional arrays?
		
		Arpad -
		Perhaps no one on this list has tried/wanted multi-dim arrays.
		
		If it's supported in 1364-200x, then again, I would expect
		that some vendors of AMS simulators would have upgraded
		the AMS side to go along with the digital standard, and
		it would work.
		
		I'm fairly sure the LRM doesn't include the syntax, but
		you can read as well as the rest of us.
		
		-Geoffrey