Re: Analog function question

While on the one hand I'd like one tool, one language
to work in.. I think this may really be impractical,
and instead think we should work towards defining how
the different languages SHOULD interact.. so that we
can know what the behavior is if we use a
SystemVerilog-AMS verification component or PSL-AMS
assertion - or a connect to a SystemC component that
implements a Matlab module.. 
that's my two cents as a "Design Verifier" using these
tools now! (but probably not a "voting" member of this
committee!)

Jonathan David
Scintera Inc.

--- Kevin Cameron <kevin@sonicsinc.com> wrote:

> Muranyi, Arpad wrote:
> 
> >Thank you all for answering this question for me.
> >Unfortunately this was the answer I suspected.
> >
> >I would like to make a request that this capability
> >be added.  A function that is written to process
> >arrays is not very useful if the arrays it can take
> >as input (or return as output) must be a
> predetermined
> >fixed size.  (This is assuming that Marq's previous
> >reply was correct in saying that arrays can be
> passed
> >at all).
> >
> >What is the procedure for submitting requests?  Can
> >I (an observer) enter items in Mantis, or does it
> >have to be done by one of the "officials"?
> >  
> >
> I would suggest that you vote for the earliest
> possible integration with 
> SystemVerilog since it has those capabilities
> already. In particular: 
> old style argument and return passing for routines
> is by value which  is 
> particularly inefficient with arrays, and
> SystemVerilog allows 
> pass-by-reference
> (http://www.eda.org/sv/SystemVerilog_3.1a.pdf - Sec 
> 10.4.2).
> 
> Kev.
> 
> 
> >Thanks,
> >
> >Arpad
>
>======================================================
> >
> >
> >________________________________
> >
> >From: owner-verilog-ams@eda.org
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Marq
> Kole
> >Sent: Friday, September 16, 2005 12:28 AM
> >To: verilog-ams
> >Subject: Re: Analog function question
> >
> >
> >
> >Oops, need to correct a small mistake below: 
> >...
> >...
> >  
> >
> >>>analog function real myFunctionName;
> >>>input in1;
> >>>real  in1[1:5];    <--------- How would I know
> the size?
> >>>      
> >>>
> >...
> >...
> >I mean an argument-controlled size given the fact
> that you cannot set 
> >a parameter value from the outside. So a call: 
> >
> >  myArrayFunction(myArraySize, myArray); 
> >
> >Where myArraySize argument carries the length of
> the myArray argument 
> >cannot be handled in current Verilog-AMS. 
> >...
> >...
> >  
> >
> >>Marq Kole
> >>Competence Leader Analog Simulation, Philips ED&T
> >>    
> >>
> >
> >
> >  
> >
> 
>