Another array question

Sorry for beating the dead horse some more, but I
ran into another problem with arrays.  I need to
either resize an array or be able to declare an
array after some number crunching.

My (limited) understanding is that the size of the
array is determined at the time of the declaration
and cannot be changed during simulation.  Correct?
Do all declarations have to be placed before the
"analog begin" keyword?  Also, my understanding is
that all code has to be after the "analog begin"
keyword.  Is this correct?

If this is all true, it doesn't seem to be possible
to run some code and generate an array which has
a size that depends on the outcome of that code.

Here is an example why this would be important:
There are two or more x-y data tables which must be
processed by some algorithm.  In order to process
them, they must have a common distribution of x-axis
points, but the raw incoming data is not guaranteed
to obey that rule.  So I need to generate a new x-axis
which includes all x-points of all tables without
repetition, and then fill in the missing y points
by interpolation.  The length of the new array will
be determined by the raw data tables, and is unknown
beforehand.

Could anyone tell me whether this can be done according
to Verilog-AMS LRM v2.2?

Thanks, and have a good weekend.

Arpad
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