Graham, In a Verilog-AMS environment, one could use the final block next to the analog block; there would be no need to do the same thing in @final_step. In pure Verilog-A on the other hand, the combination $finish and @final_step have currently different semantics than in pure digital SV the combination $finish and final block. It would break a lot of existing code to change the current Verilog-A behavior. Even though it is not possible to change the values of analog port variables anymore in the @final_step, one can still read them, and write them out to file - a file that is not necessarily open if $finish is called early (say in the @initial_step). analog begin @(initial_step) begin if (Vx < 0) begin $strobe("Vx is smaller than 0, aborting ..."); $finish; end fp = $fopen("output.tbl"); end @(final_step) $fstrobe(fp, "Vout = %g, V(out)); end final begin $strobe("$finish called ..."); end As the final block and the @final_step event are different animals, I do not see a reason to make their behaviors equivalent - one is handled by a continuous-time solver, the other by a discrete event handler. In summary: if you need postprocessing after a $finish, you can add a final block (in SV-AMS), if you want the simulation to stop immediately, use a @final_step event. Regards, Marq Marq Kole Competence Leader Analog Simulation, Philips ED&T Helwig Graham-A11558 <Graham.Helwig@freescale.com> Sent by: owner-verilog-ams@eda.org 26-10-2005 02:51 To Chandrasekaran Srikanth-A12788 <Srikanth.Chandrasekaran@freescale.com> cc verilog-ams <verilog-ams@eda.org> Subject Mantis 850: final step Classification Hello Sri, There was some discussion about how @final_step should behave w.r.t. $stop and $finish system tasks. System Verilog v3.1a has defined a final block (similar to initial blocks). For example: final begin $display("$finish has been called."); end It would reasonable to make digital final block and analog @final_step event behave the same way. Regards GrahamReceived on Thu Oct 27 07:25:22 2005
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