Verilog-AMS question regarding retention - related issue

 
The thread on retention brought up another issue that I think should be
considered.

That is how interleaved contribution statements should be handled; e.g;

analog begin
V(out) <+ 1.0;
I(out) <+ 1.0;
V(out) <+ 1.0;
end

Section 5.3.1.2 of the LRM v2.2 says;

"A statement is evaluated as follows for source branch contributions:
1. The simulator evaluates the right-hand side.
2. The simulator adds the value of the right-hand side to any previously
retained value of the branch for later assignment to the branch. If
there are no previously retained values, the value of the right-hand
side itself is retained.
3. At the end of the simulation cycle, the simulator assigns the
retained value to the source branch."

Section 5.3.1.3 of the LRM v2.2 says: 
 
"Contributing a flow to a branch which already has a value retained for
the potential results in the potential being discarded and the branch
being converted to a flow source.
Conversely, contributing a potential to a branch which already has a
value retained for the flow results in the flow being discarded and the
branch being converted into a potential source. This is used to model
switches. It is illegal to contribute to an external switch branch from
within an analog block."

This suggests that the branch should have a value of 1.0 V not 2.0V  -
what are other people's take on this?

What ever the resolution I think it would be good to have an example to
clarify this point.

Thanks,
--Martin