Re: Verilog-AMS question regarding retention - related issue

Marq/Martin -
I agree: 1.0 is correct.

Section 5.3.1.3 could perhaps be clarified a little by saying
how "the potential being discarded" means that for subsequent
source branch contributions, there is no retained value.

In addition to Martin's example, it might be interesting to 
show how one could use the retaining feature, eg with

I(res) <+ V(res) / R;
I(res) <+ white_noise(4*`P_K*$temperature / R, "thermal");

which would allow one to group all the deterministic
contributions separately from all the noise contributions
of a more complicated module.

-Geoffrey


Marq Kole wrote:
> 
> Martin,
> 
> My take would also be that the final result would be 1.0 V. The begin-end denote a sequential block, so the order of the statements should be maintained. The sections from the LRM you quote do not contradict each other. I think your example excellently shows the issue.
> 
> The actual problem is of course with users that try to "outsmart" the compiler/simulator and define a couple of contribution statements in parallel in the hopes that the overall result will be faster/better/smaller/etc. That only works if there are separate branches created for each parallel contribution statement - maybe that should be stated in the LRM as well.
> 
> Marq
> 

Martin's original example:
> analog begin
> V(out) <+ 1.0;
> I(out) <+ 1.0;
> V(out) <+ 1.0;
> end