Jonathan David wrote: >Helwig, > >Other than the confusion on p2 (Logic or wreal?) >I don't know if "3.1" is the voltage or the current on >the electrical port.. >Assuming this would be a shortcut for >electrical net01 >V(net01) <+ 3.1; >example I2 (`1b1, 0.1, net01); >so you would need to provide something like.. >example I2 (`1b1, 0.1, electrical(V(3.1)) ); > > Good idea. You probably need to add that a single (constant?) potential or flow contribution can be treated as a driver of wreal. Kev. >--- >In general this could be setup.. but I think >you would need to provide more than the value.. >you need the discipline, and the nature you are >setting. It could be more valuable for the >wreal side, but I'm not sure if its that big a help >to testbench developers.. but I guess if it were >in the language, I'd use it occasionally. >Jonathan > >--- Helwig Graham-A11558 <Graham.Helwig@freescale.com> >wrote: > > > >>Hello, >> >>The Verilog language seems to allow the connection >>of a 4-state value to discrete input port within a >>module instantiation. See the first port connection >>in the example below. This type of port connection >>is very useful. The syntax of port connections in >> >> >> module example(p1, p2, p3); >> input p1; logic p1; wire p1; >> input p2; wreal p2; >> input p3; electrical p3; >> endmodule >> >>NOTE: The static values in these wreal and >>continuous input port connections are handled in the >>same way as initialization values in explicit wreal >>and continuous net declarations. >> >>Should the merged Verilog-AMS/2005 LRM support the >>static connections to all types of input ports? >> >>Regards >>Graham Helwig >>AMS Verification Engineer >>Australia SoC Technology Centre >>Freescale Semiconductor >> >>Phone: +61-8-81683532 >>Fax: +61-8-81683201 >>Email: graham.helwig@freescale.com >> >> >> > > > >Received on Mon Nov 28 09:19:44 2005
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