Arpad - At the risk of annoying you by telling you things that aren't in the LRM ... 1364 (digital) Verilog doesn't have any idea of a dc sweep, in particular parameter sweeps. There is a proposal from Cadence somewhere in Mantis or the open issues list for something called "dynamicparam" which would be allowed to change during a dc sweep. I'm against such a proposal, because then by default "parameters" would not be allowed to change, which would make life difficult for analog designers who like to change everything as well as for characterization engineers to vary all the parameters to get a transistor model to fit the data (or else all the model-writers would have to go through their models and change every "parameter" to "dynamicparam"). Digital Verilog understands parameters to be a sort of constant. However, since you can have different values for different instances (and even override those values in various ways), the simulators must somehow take into account that parameters aren't constants like "3.0" and thus optimization must be handled differently. Verilog people often talk about "elaboration" which is a phase in which all the parameter values are set (among other things). As noted in Kevin's and Jonathan's responses, it is left to the simulator to decide if/when to compile, and thus what optimizations happen when. The analog simulators I've used with Verilog-A that compile modules do allow the parameters to be changed and swept without recompiling, just as they do for transistor models that are built-in. -Geoffrey "Muranyi, Arpad" wrote: > > Happy New Year to everyone! > > I have a question about the compilation of modules. Let's > take an example which is a model for a resistor, in which > the resistance value is parameterized. > > 1) Does this module have to be re-compiled for every value > of the parameter value (in multiple instances in the same > simulation, or in the same instance of a sweep simulation)? ... > > 5) Any related comments, cautions, suggestions?Received on Wed Jan 4 04:20:47 2006
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