Agenda for committee meeting (March 21st)

Time: 21st March 2006, 1:30pm US PST

Agenda:
* Current status
   - Status of LRM2.3 (BNF, merged lexical section, compiler directives etc)
   - Individual chapters update
   - Editable version of 1364-2005 for merger

* How to proceed from here
   - What are current deadlines, Accellera goals
   - Need to reset goals, timelines
   - Look at alternative strategies if possible, to make SV integration

* New issues that have been raised (dont think there are any mantis items)
   - if time permits in tomorrow's call?
   - Valid Numeric suffixes for Verilog-AMS
   - constant functions in system calls
   - Discipline vs Signal name conflicts
   - Request for SV's pass-by-reference to be incorporated in AMS
   - Any others (i might have missed some discussions)

Regards,
Sri
-- 
Srikanth Chandrasekaran
DTO, Tools Group
Freescale Semiconductors Inc.
Ph: +61-(0)8-8168 3592 Fax: x3201