analog generate-conditional

All,

Before making an entry in the Mantis database for a enhancement request, I 
would like to put this up for discussion.

For a certain process technology, we would like to use a bipolar model 
with selfheating code, the Mextram 504. To prevent using the self-heating 
code in absence of thermal modelling, we are looking for a solution where 
based on the value of a parameter -- related to the thermal conductance -- 
either the Mextram 504 model with self-heating or without self-heating is 
selected.

At least one simulator has a construct called a "structural if" which 
allows the selection of one branch implementation over another based on a 
conditional expression that can be determined at elaboration time, i.e. a 
constant expression. Verilog-D (at least in the 2001 incarnation) has a 
variant of the generate statement (the generate conditional in section 
12.1.3.3 of the 1364-2001 LRM) that would effectively do exactly this.

The generate statements from section 12.1 of the 1364-2001 LRM are not 
applicable as part of the Analog Subset as defined in Annex C of the 
Vedrilog-AMS LRM. As the constant expressions used in the generate 
statements are defined in the 1364 standard, they are unaware of the 
analog constant expression, i.e. allowing analog system functions such as 
$port_connected and $param_given, or the analysis functions that are 
allowed in analog constant expressions.Therefore, it would be necessary to 
define an analog equivalent of the generate statements, but unlike the 
obsoleted analog generate statement in Verilog-AMS LRM Annex C.19.3 it 
operates on instance statements instead of analog statements.

Unfortunately, the prior existence of the analog generate statement inside 
the analog block makes it hard to define an analog generate statement 
outside the analog block as distinguishing between the two can be quite 
complicated. Apart from this the advantage is that there is already a 
parallel with the analog function. So, for example:

module mex504(c, b, e, s, th);
inout c, b, e, s, th;
electrical c, b, e, s;
thermal th;
parameter real rth0 = 0.0;

analog
  generate
    if ($param_given(rth0))
      m1 #(.rth0(rth0)) mextram504sh(c, b, e, s, th);
    else
      m1 mextram504(c, b, e, s);

endmodule // mex504

which can only be distinguished from an analog block with an (obsolete) 
analog generate statement when the instance statements are seen by the 
compiler/interpreter.

Your comments are appreciated.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T