Latest merged syntax

Hello,

The latest merged syntax PDF and frame document is available that the 
following links:

    http://www.eda.org/verilog-ams/htmlpages/public-docs/merged_syntax.pdf
    
http://www.eda.org/verilog-ams/htmlpages/public-docs/merged_syntax_v1.1.pdf

Change bars in this document are w.r.t the following document:

    
http://www.eda.org/verilog-ams/htmlpages/public-docs/merged_syntax_v1.0.pdf

Below itemizes the changes to this version of the document.
1) Added hierarchical net identifier to the net_assignment syntax item 
to support coercion as seen in section 8.4.4.3. Need to add additional 
semantic constraints into the LRM to allow the following:

        electrical top.inst.net1;
        logic top.inst.net2;

 and disallow the following:

       assign top.inst.net3 = ........ ;
       force top.inst.net4;
       wire top.inst.net5;
       wreal top.inst.net6;
       ground top.inst.net7;

2) Option 2nd and 3rd arguments for Laplace and zi filter functions
3) Added missing file_path_spec syntax item section A.1.1.
4) Made the analysis name argument of the ac_stim() function optional.
5) Compiler directive syntax removed
6) Some text alignment changes in the discipline, nature and connectrule 
declarations

Below are some outstanding issues that impact the syntax:
1) Extensions ot the scale_factor syntax item in section A.8.7
2) Addition of notes preventing whitespace between selected syntax items

Regards
Graham

-- 
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Graham Helwig
AMS Verification
Australian Semiconductor Technology Company (ASTC) Pty Ltd

Location: 76 Waymouth St, Adelaide, SA, 5000, Australia
Phone     +61-8-82312782
Moblie:   +61-4-03395909 
Email:    graham.helwig@astc-design.com
Web:      www.astc-design.com
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