Re: Syntax chnages for the analysis() function

Graham,

I think it is too much of a restriction to only use analysis_function_call 
in a conditional by itself. For example, If I know a model gives problems 
in DC convergence in certain circumstances (for instance, a parameter 
having a valid but awkward value) and I want the model to help in that 
situation, I would like to be able to write:

analog begin

  if (analysis("nodeset") && shaky_param < 0)
    V(inp) <+ 0.707;

end

Of course, you could also use nested if-statements, but it would be hard 
to explain to language users what the difference is.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T










Graham Helwig <graham.helwig@astc-design.com> 
Sent by:
owner-verilog-ams@eda.org
12-04-2006 07:21

To
VerilogAMS Reflector <verilog-ams@eda.org>
cc

Subject
Syntax chnages for the analysis() function
Classification







Hello,

 From the committee call today, was there a decision to separate 
analysis() function syntax from the analog operator syntax. In the 
latest merged syntax, this is already done. See analysis_function_call 
and analog_filter_function_call syntax in section A.8.2. There was some 
discussion about giving these syntax items more descriptive names. Was 
there a decision made what these more descriptive names will be?

After analyzing the latest merged syntax, the analysis_function_call 
syntax needs to be moved from the constant_expression syntax into the 
analog_expression syntax because I discovered that the following is not 
supported:

    analog begin
         if (analysis("static")) begin
             .........
          end
    end

By placing analysis_function_call syntax into the analog_expression 
syntax, analysis() function calls can be used in any statement 
(containing analog_expression syntax) within an analog block. Is this 
desirable?

If the analysis() function should only appear by itself within analog 
conditional statements (like the example above), then this restrictive 
usage can be captured by modifying the analog_conditional_statement 
syntax instead of the analog_expression syntax. Is this a reasonable 
restriction?

Regards
Graham



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