Re: Question on encryption

Verilog added IP protection in the latest version. Verilog-AMS should adopt this instead of creating its own.

David
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David W. Smith
Synopsys Scientist
W: 503.547.6467
M: 650.861.9814

-----Original Message-----
From: owner-verilog-ams@eda.org <owner-verilog-ams@eda.org>
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Mon Apr 24 11:22:37 2006
Subject: Question on encryption

Hello everyone,

Sorry for bringing up such off topic questions all the time,
but I would like to find out whether encryption has been
considered by the workgroup for Verilog-AMS models.

The reason I am asking is because this has been brought up
in the recent IBIS Open Forum discussions in connection
with modeling bleeding edge high speed buffers behaviorally.
Semiconductor vendors feel increasingly uneasy about
releasing even behavioral models for such buffers without
encryption.  In addition we do not like the idea of using
the individual and proprietary encryption schemes of EDA
vendors, because that would require the model makers to
encrypt the same model multiple times for each tool.  It
seems that there is a strong need for some sort of a tool
independent encryption scheme.

We thought we should look around what has been done, if
anything, before we reinventing the wheel.

Thanks,

Arpad
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