Mantis item 1405: Using current signal-flow disciplines

Hello,

The Mantis 1405 text is:

 > There is a problem in the LRM involving flow-type signal flow 
disciplines that
 > I have been trying to get corrected. Currently, if there is only one 
nature in a
 > discipline, it must the potential. This restriction is undesirable 
because it prevents
 > one from using signal-flow disciplines for currents. They actually 
give an example
 > of a current signal flow discipline in the LRM, but the current is a 
potential and
 > so would be forced to satisfy KPL rather than KFL. This prevents one 
from
 > connecting signal current signal-flow terminals to electrical nets, 
thereby damaging
 > one of the nicer features of the language. Could you please remove 
the restriction
 > ([sec 3.4.2.1] page 38) and change the example so that the 
signal-flow current is
 > a flow?

Looking at version 1.0 of the Verilog-A LRM the type of signal-flow 
disciplines that Ken is looking for was supported, but now they are not. 
Does anyone recall what the rationale was for the change?

Ken, are you wanting to connect current signal-flow branches directly 
into a conservative branch loops (just like voltage signal-flow 
branches)?  For example:

         module source (net);
           current net;
           analog I(net) <+  ................;
        endmodule         

       module top;
          electrical gnd;
          ground gnd;
          source src(n1);
          resistor #(.r(10K)) r1(n1, n2);
          resistor #(.r(1K)) r2(n2, gnd);
       endmodule

Regards
Graham

-- 
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Graham Helwig
AMS Verification
Australian Semiconductor Technology Company (ASTC) Pty Ltd

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