Jonathan, In response to your email to Peter: I would not even expect a signal flow flow nature to follow the KCL. As an example: the following signal flow block does not obey the KCL: `include "disciplines.vams" discipline current; flow Current; enddiscipline; module current_mult (in, out); inout in, out; current in, out; parameter real mult = 2; analog I(out) <+ mult * I(in); endmodule In a conservative system the potential and the flow are linked, where one obeys the KCL, and the other the KVL. Because conservation is absent in a signal flow system, the actual distinction between a potential and a flow is also absent. The only relevant thing in such a discipline is the value. That is why limiting the nature in signal flow disciplines to potential only is a mistake. Both flow and potential would fit equally well. To make a connection between a conservative system and the above current multiplier I assume a separate (connect)module would be needed that assures conservation on the conservative side. Marq Marq Kole Competence Leader Analog Simulation, Philips ED&T Jonathan David <jb_david@yahoo.com> Sent by: owner-verilog-ams@server.eda.org 31-05-2006 01:36 To Peter Liebmann <peterl@xpedion.com> Sri Chandra <srikanth.chandrasekaran@freescale.com> cc Verilog-AMS LRM Committee <verilog-ams@server.eda.org> Subject Re: Agenda for committee call - 30 May 2006 Classification Resending my response to peter back to the list: I would expect both of those expressions to fail a syntax check, due to using the output value on both the left hand and right hand side of the equation.. To do that I think you need to use the "IMPLICIT" form.. V(n1) : 2*V(n1)+6 = 0; which I would read: (the Voltage on n1 is defined such that 2*V(n1)+6 = 0; You could model a resistor divider from n1 to n2 in two ways: conservative: V(n1,n2) <+ R1* I(n1,n2); V(n2) <+ R2*I(n2); // gnd is implicit reference // handles non-zero current flow out of n2 into other circuitry signal flow potential V(n2) <+ V(n1)*R2/(R1+R2); //Assumes I(n2) ~0 // but the voltage is the same even if its not.. But While I would expect a signal_flow (flow) nature to follow KCL: without the accompanying potential we can hardly call it conservative. its either CONSERVATIVE (Potential & FLOW) or its SIGNAL FLOW (Potential or Flow).. never both. an example: --- so if the SOURCE model has module top; electrical extres; voltage vbandgap; current iref; source REF (.n1(iref), .vbg(vbandgap) .res(extres)); resistor #(.r(12K)) Rext (extres,gnd!); load DUT (.ibias(iref)); endmodule module source (n1, vbg, res); output current n1; output voltage vbg; output electrical res; analog begin V(vbg) <+ 1.20; V(res) <+ 1.20; // 1.2v/12K = 0.1m = 100uA // out => -100mA I(n1) <+ I(res)/2.0; // -50ua end module load (ibias); input current ibias; real Ibias; analog begin @timer(0,10m) begin $strobe("INFO: %M: Ibias = %g at %g\n", I(ibias), $abstime); end end endmodule I Should get INFO: top.DUT: Ibias = 5.00e-5 at 0.000 INFO: top.DUT: Ibias = 5.00e-5 at 1.00e-5 ... in the log file. Showing that the current OUT of the Source = the current INTO the load (and "into" is the positive current direction, even for output pins.. ) In my view, a single module in Verilog is useless.. its the interconnection of multiple modules that is useful.. Jonathan --- Peter Liebmann <peterl@xpedion.com> wrote: > I have a question about signal flow with a flow > nature. Is it conservative? > The reason I ask if one has a signal flow potential > nature , the solution > to a simple equation with only one source at n1, > > V(n1) <+ 2*V(n1) +6; > > is obviously -6. > > However, if n1 is a signal flow flow nature and is > conservative, > > I(n1) <+ 2*I(n1) +6; > > has no solution since I(n1) must sum to 0 and there > is only one source > at n1. > > Is this what we want? > > Peter Liebmann > > > Sri Chandra wrote: > > > > Time & Date: 30 May 2006, 3pm Pacific > > Dialin: 1-877-346-8823 (US - toll free) > > 1-203-320-0407 (Intl) > > Pin: 602538 > > > > > > * Review of chapter 2 - lexical tokens with > updated syntax (Graham) > > > > cheers, > > Sri > > > >Received on Wed May 31 01:15:48 2006
This archive was generated by hypermail 2.1.8 : Wed May 31 2006 - 01:16:00 PDT