Re: Merged version of chapter 6

Ken -
The problem is, I think, deeper than you indicate.  It's not just that
the LHS can't use a port access function, but also that V(<d>) is not
allowed per the LRM (section 5.1.4, page 98 of LRM 2.2):

  The expression V(<a>) is invalid for ports and nets, where V is a
  potential access function.

The LRM says what I(<a>) means, but nowhere do we have an explanation
of what V(<a>) would mean.

-Geoffrey


Ken wrote:
>> 1. On the top of page 112 it says "The left-hand side shall not use a
>> port access function from Section 5.1.4.". I'd sure like to get rid of
>> that restriction. As a restriction it does not provide any real benefit,
>> but it does take away a nice capability. For example, if I had the
>> ability to assign to a port branch, then I could easily make a series
>> resistor or inductor using
>>     V(<d>) <+ rd*I(<d>) + ld*ddt(I(<d>);
>> This is nice for semiconductors because it eliminates that whole
>> internal node/external node confusion. It also makes it easy to add
>> series parasitics from outside an existing module without modifying the
>> module or knowing anything about its internal structure
>>     V(<inv.out>) <+ rout*I(<inv.out>);
>> I believe that one can already do this with shunt parasitics, but not
>> with series parasitics. This addresses that inconsistency.