Re: Verilog-AMS committee Agenda

The call time is 7:00am Pacific.

cheers

Jonathan David wrote:
> What time is the call?
> 
> ----- Original Message ----
> From: Sri Chandra <srikanth.chandrasekaran@freescale.com>
> To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
> Sent: Wednesday, July 19, 2006 8:40:10 PM
> Subject: Verilog-AMS committee Agenda
> 
> 
> Hi all,
> 
> Looks like i have not got adjusted to the new time slot for the call and 
> keep forgetting to send the agenda out. But hopefully people in US may 
> see this notification, tho' its a bit late out there and the call is in 
> the morning. The agenda is the same as what it was couple of weeks back.
> 
> Call-In Details:
>    USA Toll Free Number: 877-346-8823
>    USA Toll Number: +1-203-320-0407 (for intl)
>    Participant Passcode: 602538
> 
> Agenda:
>    * Discussion on the constant expression proposal submitted by graham 
> which addresses the issue of handling analysis functions
>    * Review of modification for nested scope parameter overrides based 
> on feedback from 1364-2005: Digital does not allowed named block 
> parameters to be overridden from module instantiation - defparams need 
> to be used for this.
>    * Start reviewing from Section 6.3.1.1
> 
> Regards,
> Sri

-- 
Srikanth Chandrasekaran
DTO Tools Development
Freescale Semiconductor Inc.
Ph: +91-120-439 4056 F: x5199