Re: Regarding support of wreal

I'm all for BETTER solutions.. 
 
I don't see the problem about the resolution function.. 
If I connect wreal to logic by accident.. I don't want the simulation to run.. 
the design is wrong. fix the design, 
then there are no more resolution issues.. 
 
Generally I can't afford to have these signals in the Continuous Time domain.. 
any other Suggestions.. ?

In this case, no solution would leave VHDL as the only available solution.
Not all nets are something you could swap a logic driver with.. 
MY complaint about the wreal solution is that CADENCE won't let me
put 10 wreals in a bus (wreal [9:0] signal_p;)
it was nearly the first AMS bug I reported on learning about wreal.. 
and they still haven't fixed it.. 
Any better AMS simulators out there? 
Jonathan 

----- Original Message ----
From: Kevin Cameron <kevin@sonicsinc.com>
To: Verilog-A Reflector <verilog-ams@eda.org>
Cc: Martin O'Leary <oleary@cadence.com>
Sent: Monday, August 7, 2006 2:12:04 PM
Subject: Re: Regarding support of wreal


Martin O'Leary wrote:

>(another perspective on the wreal feature)
>
>Wreal part of the Verilog-AMS standard not the Verilog standard and has
>been there since LRM2.0,
>released in 2000.
>
>It has proven popular with users and is supported by multiple implementors.
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>
- on the principal that a bad solution is better than no solution.

The reason that it is unnecessary is that wires should be neutral and 
have their type/discipline derived at elaboration be looking at the 
drivers/contributions. A wreal is essentially a wire with a driver of 
type real (a non-resloved type). As far as I remember you can't connect 
wreal to anything else so it breaks the plug-and-play approach intended 
in the original design of the language - i.e. you should be able to swap 
a "digital" module with a real driver for an analog module with a 
contribution and have it handled automatically.

Kev.

>Thanks,
>--Martin 
>
>-----Original Message-----
>From: owner-verilog-ams@eda-stds.org
>[mailto:owner-verilog-ams@eda-stds.org] On Behalf Of Kevin Cameron
>Sent: Monday, August 07, 2006 1:14 PM
>To: Dave Miller
>Cc: verilog-ams@eda-stds.org
>Subject: Re: Regarding support of wreal
>
>
>wreal was a (unecessary) Cadence hack that only exists in Verilog-A[MS].
>
>Hopefully it will go away some day.
>
>Kev.
>
>Dave Miller wrote:
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>
>>Hello all,
>>I am a bit confused about the support of the net type 'wreal'. I see 
>>that it is included in the AMS syntax that Graham has done but I can't
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>>find any mention of 'wreal' in 1364-2001, or 1364-2005. Is 'wreal' a 
>>type that is only valid in the digital domain (i.e. can only assign to
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>>it in digital), if so why can't I find it in the digital LRM's or am I
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>>looking in the wrong place?
>>Thanks for any help,
>>
>>Regards
>>Dave
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