Hello, Regarding the discussion about analysis() function usage in the language, the file http://www.verilog.org/verilog-ams/htmlpages/public-docs/merged_syntax_constantAnalogExpression.pdf has been updated the event_expression and analog_event_expression syntax to use common syntax for cross, timer and above event functions. These analog event functions use constant_expression instead of analog_constant_expression. Also, there was discussion about restricting analysis() function call to be used within analog conditional and case statement's expressions. The http://www.verilog.org/verilog-ams/htmlpages/public-docs/merged_syntax_constantAnalogExpression_alternative.pdf file defines the syntax for this restricted usage of the analysis() function. Regards Graham -- ========================================================== Graham Helwig AMS Verification Australian Semiconductor Technology Company (ASTC) Pty Ltd Location: 76 Waymouth St, Adelaide, SA, 5000, Australia Phone +61-8-82312782 Moblie: +61-4-03395909 Email: graham.helwig@astc-design.com Web: www.astc-design.com ==========================================================Received on Tue Aug 8 17:58:51 2006
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