Re: analysis("nodeset")

Geoffrey,

The table suggests that the analysis("nodeset") return value is always 
true for DC, where in fact it is not. There is undesirable room for 
ambiguity in this table.

One particular example wen you need only a temporary enforcement is in the 
initialization of a feedback oscillator or providing an initial state for 
a flipflop or other memory device. The table says you cannot make this 
distinction by using analysis("nodeset"), but I think this is the purpose 
of this particular piece of Verilog-A.

Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T










"Geoffrey.Coram" <Geoffrey.Coram@analog.com> 
Sent by:
owner-verilog-ams@server.eda.org
25-08-2006 14:50

To
Marq Kole/EHV/RESEARCH/PHILIPS@PHILIPS
cc
verilog-ams <verilog-ams@server.verilog.org>
Subject
Re: analysis("nodeset")
Classification







Marq -
Nodesets are enforced for more than the very first iteration.
They are enforced, via a voltage source and a small resistor,
for as many iterations as are required to get "convergence";
then they are removed and further iterations are performed
until true convergence is obtained.

I believe the table is not misleading.

-Geoffrey


Marq Kole wrote:
> 
> All,
> 
> In the Verilog-AMS LRM 2.2, section 4.5.1, specifically table 4-25 the 
"nodeset" argument refers to the "First part of "static" when nodesets are 
enforced" and then continues to give values that are identical to an 
initial_step event. However, this table is misleading as the 
analysis("nodeset") should only return true for the very first iteration 
of the Newton process for finding the DC solution -- the exact moment the 
nodesets are enforced.
> 
> I think this needs to be made more explicit, either by changing the 
table to make the Newton process explicit, or by adding a paragraph 
explaining the "nodeset" argument.
> 
> Marq