support for multiple supplies

All,
    I saw the article in the EE-Times insert "EDA Tech Forum" by Strahle
and Gossman from Infineon on using VHDL-AMS to find issues in designs
that stem from having multiple power supplies. Their approach seemed a
bit crude, so I thought I would try using the Verilog-AMS natures and
disciplines to try to provide a more elegant solution. What I wanted at
a minimum was to prevent from connecting gates that operate at one
supply voltage from being connected gates that use another supply
voltage. So I tried to define new disciplines as follows ...

discipline logic1p2
    domain discrete;
enddiscipline
discipline logic1p5
    domain discrete;
enddiscipline

module inv1p2 (out, in);
    output out;
    input in;
    logic1p2 out, in;

    assign out = !in;
endmodule

module inv1p5 (out, in);
    output out;
    input in;
    logic1p5 out, in;

    assign out = !in;
endmodule

module testbench;
    logic1p2 n1;
    logic1p5 n2;

    inv1p2 I1 (.out(n2), .in(n1));
    inv1p5 I2 (.out(n1), .in(n2));
endmodule

Verilog-AMS then allowed me to connect together ports with two different
disciplines because apparently they are compatible. So question number
one ...

Q1: Is there a way of explicitly declaring that two disciplines are
incompatible? Perhaps ...
    connectrules multisupply;
        connect logic1p2, logic1p5 resolveto error;
    endconnectrules
or
    connectrules multisupply;
        connect logic1p2, logic1p5 resolveto error("you must connect
1.2v logic to 1.5v logic");
    endconnectrules


So then I tried using connect modules, by adding the following to the
above example ...

connectmodule logic1p2to1p5 (out, in);
    output out;
    input in;
    logic1p5 out;
    logic1p2 in;

    initial $stobe("ERROR: %M: 1.2v logic driving 1.5v logic");
    assign out = 1'bx;
endmodule

connectmodule logic1p5to1p2 (out, in);
    output out;
    input in;
    logic1p2 out;
    logic1p5 in;

    initial $stobe("ERROR: %M: 1.5v logic driving 1.2v logic");
    assign out = 1'bx;
endmodule

connectrules multisupply;
    connect logic1p2to1p5;
    connect logic1p5to1p2;
endconnectrules

But this does not work because connect modules must have exactly one
discrete port and one continuous port. So question number 2 ...

Q2: Why have this restriction. Why can't we support connect modules that
have two discrete ports or two continuous ports?

Does anybody have any suggestions on how to prevent logic gates from
different supply domains from being connected together?

Thanks,
-Ken