Verilog-AMS Committee Meeting Minutes - Sept 28 2006

Martin O'leary - Cadence
Jim Barby - University of Waterloo
Patrick O'Halloran - Tiburon
Boris Troyanovsky, Tiburon
David Miller - Freescale
Sri Chandra - Freescale
Muranyi Arpad - Intel
Michael Mirmak - Intel
Jonathan David - Consultant

Michael Mirmak inquired whether Verilog-AMS was planning to implement a 
common crypt/decrypt functionality. Verilog and System Verilog already 
have this feature, so will System Verilog-AMS. It would be best if we 
implemented this feature based on the System Verilog-AMS approach. We 
just need to decide if we will push to add this to LRM 2.3 since it is 
mentioned as part of Annex H in 1364-2005 Verilog Standard.

Continued review of Chapter 4 - Expressions resuming from section 4.3 
going through to section 4.4.9
The following corrections were noted.

section 4.4 - The section name was changed to Analog Filters to keep in 
sync with the new BNF, however it was decided that it would be better to 
leave it as analog operators as that is what people are used to.

section 4.4.1 - Would prefer if the last sentence of the first paragraph 
read: ""no state history prior to time t == 0".
Also move this section to the end of Section 4.4. That way people will 
first learn about the analog operators. By the time they reach the 
section on the restrictions, they may make more sense.

section 4.4.2 - Spelling mistake in last sentence: constsant vs constant.

section 4.4.5 - There was some discussion as to what happens when the ic 
expr is not calculated during the ic step. Should the ic expression 
always be evaluated, even if the idt() is not? (due to it being inside 
an if(analysis("static") block for example). Will leave this for the 
time being as there may be further changes required to idt()/idtmod() to 
clarify some of the ambiguities.
Reword the first sentence of the second paragraph that discusses when 
the ic value will be used. "idt() returns the value of the initial 
condition if performing a DC or IC analysis, or whenever assert is given 
and is non-zero."

section 4.4.6 - Make sure that idtmod() is consistent with any changes 
made to the idt() section.

section 4.4.8 - Need to try and clarify how the td argument is handled 
when the max_delay argument is and isn't present. Also get rid of the 
last sentence in the first paragraph as it is wrong.
Also discussed whether an error should be raised if td > maxdelay, or if 
maxdelay should just be used under that condition. Refer to email sent 
to reflector:
  Date: Tue, 03 Oct 2006 09:33:45 -0500
  From: Dave Miller <David.L.Miller@freescale.com>
  To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
  Subject: Question on absdelay

For next meeting, will continue review starting at section 4.4.9 
Transition Filter.

Next meeting scheduled for Date & Time: 5 Oct 2006, 7:00am Pacific
Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

Cheers...
Dave

-- 
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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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