RE: idt reset issue

Ken,

    The assert argument in idt can be bias dependent. (Is that correct?)
So it takes a solution on one step to determine that idt should be reset
and then only the next step can use the new reset idt value.  We would
have to specify a way of resolving on the same step with the new idt
value.

Ilya

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Geoffrey.Coram
Sent: Wednesday, October 04, 2006 1:18 PM
To: VerilogAMS Reflector
Subject: idt reset issue

Resending for Ken Kundert; original message bounced (too long).
Attachment has been saved as
http://www.verilog.org/verilog-ams/htmlpages/public-docs/idt-issue.pdf


----------------- Original Message ------------- All,
    I'd like to join the meeting tomorrow and discuss the reset feature
of the idt function. I have not had much luck using this feature through
the years, and recently had a situation where I really needed it.
Unfortunately, I found the Cadence implementation unsuitable once again,
and when I dug in to it I found the LRM silent on critical aspects of
this feature. I have attached a very short document that illustrates the
issue and proposes what I believe to be the desirable behavior. If you
all agree I will work on coming up with the needed modifications to the
LRM.

-Ken