Dave, this restriction may have been because we thought that 1364 didn't allow functions to appear in a parameter context. However I understand form one our Verilog experts this has been and 1364 supports this with restrictions (see 10.3.5 of the 1364-2001) Thanks, --Martin -----Original Message----- From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Dave Miller Sent: Tuesday, October 10, 2006 8:55 AM To: Verilog-AMS LRM Committee Subject: Clarification Regarding Constant Analog UDF's Hello Graham, Hello all, During last weeks call I inquired as to why we don't allow constant analog user defined functions within the new revised BNF. Unfortunately I didn't properly document the reasoning that was given and now I can't remember. Would it not also be a good idea to allow constant analog UDF's? I was thinking this would be useful also in a analog only context as it would give the option of assigning a complex expression to a parameter using a analog UDF instead of using a macro function for example. This would allow more flexibility for the user. Regards Dave -- ===================================== -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 =====================================Received on Tue Oct 10 20:47:38 2006
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