RE: Clarification Regarding Constant Analog UDF's

The statement restricts constant function definitions from containing
constant function calls only where a constant_expression is required.
The reason is to avoid circularity of the function calls. See They
http://boydtechinc.com/btf/archive/btf_1999/0745.html .

Shalom

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-
> ams@server.eda.org] On Behalf Of Bresticker, Shalom
> Sent: Wednesday, October 11, 2006 6:21 PM
> To: Dave Miller; Martin O'Leary
> Cc: Verilog-AMS LRM Committee
> Subject: RE: Clarification Regarding Constant Analog UDF's
> 
> The statement is correct. I'll explain later.
> 
> Shalom
> 
> > -----Original Message-----
> > From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-
> > ams@server.eda.org] On Behalf Of Dave Miller
> > Sent: Wednesday, October 11, 2006 6:18 PM
> > To: Martin O'Leary
> > Cc: Verilog-AMS LRM Committee
> > Subject: Re: Clarification Regarding Constant Analog UDF's
> >
> > Hi Martin,
> > Okay so since we want to try and stay in sync with Verilog 1364,
then
> > sounds like we can also allow constant analog user defined
functions,
> as
> > well as recursively calling a analog UDF (I can do this in digital).
> >
> > The restrictions on constant functions that digital mentions in
10.4.5
> > (1364-2005) seem okay and we can adopt them where necessary although
I
> > can't think of any statements that are allowed in an analog UDF that
> > couldn't be used in a constant context.
> > However I don't understand the last restriction that digital
mentions:
> > " - They shall not themselves use constant functions in any context
> > requiring a constant expression."
> >
> > I wonder if that is a typo and should read "They shall themselves
use
> > ....." as it seems strange to restrict a constant function from
using
> a
> > constant function.
> >
> > Cheers...
> > Dave
> >
> > Martin O'Leary wrote:
> > > Dave,
> > > this restriction may have been because we thought that 1364 didn't
> > allow
> > > functions to appear in a parameter context.
> > >
> > > However I understand form one our Verilog experts this has been
and
> > 1364
> > > supports this with restrictions (see 10.3.5 of the 1364-2001)
> > >
> > > Thanks,
> > > --Martin
> > >
> > > -----Original Message-----
> > > From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org]
> On
> > > Behalf Of Dave Miller
> > > Sent: Tuesday, October 10, 2006 8:55 AM
> > > To: Verilog-AMS LRM Committee
> > > Subject: Clarification Regarding Constant Analog UDF's
> > >
> > > Hello Graham, Hello all,
> > > During last weeks call I inquired as to why we don't allow
constant
> > > analog user defined functions within the new revised BNF.
> > Unfortunately
> > > I didn't properly document the reasoning that was given and now I
> > can't
> > > remember.
> > >
> > > Would it not also be a good idea to allow constant analog UDF's? I
> was
> > > thinking this would be useful also in a analog only context as it
> > would
> > > give the option of assigning a complex expression to a parameter
> using
> > a
> > > analog UDF instead of using a macro function for example. This
would
> > > allow more flexibility for the user.
> > >
> > > Regards
> > > Dave
> > >
> > > --
> > > =====================================
> > > -- David Miller
> > > -- Design Technology (Austin)
> > > -- Freescale Semiconductor
> > > -- Ph : 512 996-7377 Fax: x7755
> > > =====================================
> > >
> > >
> > >
> >
> >
> > --
> > =====================================
> > -- David Miller
> > -- Design Technology (Austin)
> > -- Freescale Semiconductor
> > -- Ph : 512 996-7377 Fax: x7755
> > =====================================