Re: Section 7 items

From: Ken Kundert <ken_at_.....>
Date: Mon Oct 16 2006 - 14:09:24 PDT
Marq,
    The only issue I am aware of with multiple analog blocks is the
sharing of variables, much like the issue of analog block sharing
variables with digital blocks. There are race condition issues that we
have to be careful of. Presumably we would have the variables owned by a
particular analog block, but even with this there are issues. Consider
two analog blocks, b1 and b2, and two variables, v1 and v2. Assume that
v1 is owned by b1 and so can only be assigned in b1. Similarly, v2 is
owned by b2. Now assume that in b1 a value is assigned to v1 that
depends on the value of v2. Further assume that in b2 a value is
assigned to v2 that depends on v1. How does one reconcile the fact that
these two assignments are expected to occur simultaneously?

-Ken

Marq Kole wrote:
> 
> All,
> 
> I am currently working on section 7, and up till now I've encountered
> two items for which now Mantis items are available, but which I recall
> have had some serious discussions in the past:
> 1. Support for looping and conditional generator statements (IEEE
> 1364-2005, sec 12.4);
> 2. Support for multiple analog blocks within one module (related to item 1);
> (I'm not sure I have the formal names of these things right as I don't
> have the standards documents at hand)
> 
> For the first item: if only module instantiations are part of the
> generator constructs, then this could be solved without much issues
> during elaboration; however, if we also want to be able to use these
> generator constructs on analog blocks, we have to make a decision on
> item 2. I believe that in digital you can use the generator statements
> also for always and initial blocks, as well as for tasks, so the logical
> extension into the AMS domain would be to support analog blocks for this
> as well.
> 
> Is there any particular reason why multiple analog blocks would be hard
> to support? Wouldn't they just appear as (inline) subcircuits to the
> simulator kernel?
> 
> Cheers,
> Marq
> 
> 
> Marq Kole
> Competence Leader Robust Design
> 
> Research
> NXP Semiconductors

Received on Mon Oct 16 14:09:30 2006

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