RE: idt reset issue

Geoffrey,

   Yes, after thinking about this more, I agree. There is no need to
wait till the next step to perform the reset. (i.e. for well written
models).


Ilya


-----Original Message-----
From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com] 
Sent: Wednesday, October 18, 2006 12:23 PM
To: Ilya Yusim
Cc: VerilogAMS Reflector
Subject: Re: idt reset issue

Ilya -
My understanding would be: as the simulator evaluates the analog block,
it will have a value for the assert argument based on the unknowns for
the current iteration.  This will determine whether idt should be reset,
which determines the matrix load for that *iteration*.  The simulator
will have to keep iterating if the idt value changes (typically, I think
there will be an element in the vector of unknowns to keep track of
this, and the value of this element should not change more than the
tolerance from iteration to iteration).

It is, of course, possible to make a circuit that never converges, if
one isn't careful about feedback.

-Geoffrey


Ilya Yusim wrote:
> 
> Ken,
> 
>     The assert argument in idt can be bias dependent. (Is that 
> correct?) So it takes a solution on one step to determine that idt 
> should be reset and then only the next step can use the new reset idt 
> value.  We would have to specify a way of resolving on the same step 
> with the new idt value.
> 
> Ilya