Re: Verilog-AMS Committee Meeting Minutes - Nov 16 2006

LRM 2.2 says, in 7.5:
  From within an analog block, it is possible to use hierarchical
  name referencing to access signals on an external branch, but
  not external analog variables or parameters. When accessing
  external branches, a branch signal (its potential or flow) can be
  monitored (probed); for source branches, contributions can be made
  to the output signal.


So, it appears that the barn door is already open, regarding
hierarchical contributions.

However, back in 5.3.1.3, we do have one restriction:
  It is illegal to contribute to an external switch branch from
  within an analog block.

-Geoffrey



Sri Chandra wrote:
> 
> Marq, Dave,
> 
> I would agree with that comment of disallowing contributing to a analog
> net hierarchically. If we are talking implementing, from my
> understanding having hierarchical flow probes may not also be very
> trivial. Can be done but not easy.
> 
> Also it will be interesting to know how we are going to refer to
> "unnamed" branches hierarchical? I am not sure whether the syntax would
> allow that now or should it always refer to a branch already declared?
> 
> On a side note, I am guessing we will not allow any hierarchical
> references to a parameter, variable inside a named block. I think this
> is what we decided recently in one of the discussions of the committee
> meeting, just wanting to clarify that point.
> 
> Regards,
> Sri
> 
> Marq Kole wrote:
> >
> > Dave,
> >
> > The only use that I can think of for hierarchical references to analog
> > quantities is to set initial values for such quantities. Read access to
> > such quantities has no issue, but contributing to a hierachical branch
> > may have some issues that would make it hard to implement - making it an
> > obstacle to the deployment of Verilog-AMS 2.3.
> >
> > Unless we had a specific use case for contribution to hierarchical
> > analog branches, my choice would be to disallow it.
> >
> > Cheers,
> > Marq
> >
> >
> > Marq Kole
> > Competence Leader Robust Design
> >
> > Research
> > NXP Semiconductors
> >
> >
> >
> >
> >
> >
> >
> >
> > *Dave Miller <David.L.Miller@freescale.com>*
> >
> > Sent by:
> > owner-verilog-ams@server.eda.org
> >
> > 17-11-2006 16:37
> >
> >
> > To
> >       Marq Kole <marq.kole@nxp.com>
> > cc
> >       verilog-ams <verilog-ams@server.eda-stds.org>
> > Subject
> >       Re: Verilog-AMS Committee Meeting Minutes - Nov 16 2006
> > Classification
> >
> >
> >
> > One thing I forgot to ask last night, which I guess was relevant to this
> > section. What was the resolution on allowing hierarchical references to
> > analog quantities? In particular contributing to hierarchical analog
> > branches and variables? I remember there was some discussion on this
> > previously but I am not sure on what the outcome was. Are we going to
> > explicitly disallow contributing to a hierarchical analog branch?
> >
> > Dave