All,
A second update of section 7 "Hierarchical
Structures" will be available shortly from the Verilog-AMS standardization
website at:
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier.pdf
while the previous versions of the document should be available at:
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier_v1.1.pdf
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier_v1.0.pdf
The following changes have been made to the document (merged_hier.pdf)
with respect to the previously posted document (merged_hier_v1.1.pdf);
unless noted differently, these are the changes as proposed during the
November 16 conference call, noted in the minutes of that call, or noted
in email discussion outside the call.
section 7.5.1, p. 151, both examples: the analog contribution statements
have been encapsulated in an analog block.
section 7.5.2, p. 154, the remark after
the example that some of the functionality of conditional generate constructs
can be achieved through paramsets has been elaborated. It now explicitly
mentions overloaded paramsets and points to section 7.3.2 that explains
this.
section 7.5.2.1, p. 154, a new subsection
on dynamic parameters that allow an implementation to restrict the sweeping
of parameters that change the structure of a design.
section 7.8.1, p. 159, a new section
that explains the elaboration of analog blocks and the interaction of this
elaboration with the evaluation of generate constructs.
section 7.8.2, p. 159, a new section
that explains the interaction of generate constructs and paramsets.
section 7.8.3, p. 159, a new section
explaining the interaction of generate constructs and discipline resolution.
section 7.8.4, p. 159, overloaded paramset
selection inside a generate region has been explicitly added.
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Received on Tue Nov 28 07:25:57 2006
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