Re: idt reset issue

Arpad,
    The problem with the LRM is that table entry that discusses the
assert argument for idt() it says: "t0 is the time when assert last
became 0". The issue is that assert becomes 0 on the next time step, and
when that occurs is determined by the simulator and not the modeler.
That line should be changed to "t0 is the time when assert was last
nonzero". To clarify this, a figure is needed to show that how idt()
reacts to assert over time.

There are other problems with the description of the idt() operator in
the way it describes the behavior in the DC and IC analyses and the
definition of t0; it is somewhat ambiguous. I was thinking of cleaning
that up as well.

-Ken

Muranyi, Arpad wrote:
> Ken,
> 
> I agree that the reset feature of idt should work as
> you described in your document.  I am just curious,
> is this only a tool implementation problem, or is this
> an LRM problem?  I didn't see anything in your document
> on why the description in the LRM is ambiguous, and I
> didn't see a suggestion for how to correct that.  Do
> you have a proposal for a better description?
> 
> Thanks,
> 
> Arpad
> ========================================================
> 
> -----Original Message-----
> From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Ken Kundert
> Sent: Tuesday, November 28, 2006 8:26 AM
> To: VerilogAMS Reflector
> Subject: Re: idt reset issue
> 
> Sri,
>      Was there any decision made on the idt issue? Would you like me to
> a cut at refining the description of idt in the LRM to avoid the
> ambiguity in its behavior?
> 
> -Ken
> 
> Ken Kundert wrote:
>> All,
>>    I apologize for missing the call this morning. It turns out that
>> Thursday mornings are just too busy for me to attend.
>>
>> I have updated the document to include an model that patterns the
>> desired behavior. You can find the updated version at
>> http://designers-guide.org/private/vams-extensions/idt-issue.pdf
>>
>> Also, I would like to offer the use the my online forum for use by the
>> Verilog-AMS committee. We used it when defining the compact model
>> extensions and I found it to be a very convenient way to carrying on the
>> conversations about particular issues. It naturally separates the
>> discussion threads and makes them easy to follow. If you wanted to do
>> this, I would give you a private board, so only invitees would be
>> allowed to see the board or contribute.
>>
>> -Ken
>>
>>
>> Geoffrey.Coram wrote:
>>> Resending for Ken Kundert; original message bounced (too long).
>>> Attachment has been saved as
>>> http://www.verilog.org/verilog-ams/htmlpages/public-docs/idt-issue.pdf
>>>
>>>
>>> ----------------- Original Message -------------
>>> All,
>>>     I'd like to join the meeting tomorrow and discuss the reset feature
>>> of the idt function. I have not had much luck using this feature through
>>> the years, and recently had a situation where I really needed it.
>>> Unfortunately, I found the Cadence implementation unsuitable once again,
>>> and when I dug in to it I found the LRM silent on critical aspects of
>>> this feature. I have attached a very short document that illustrates the
>>> issue and proposes what I believe to be the desirable behavior. If you
>>> all agree I will work on coming up with the needed modifications to the LRM.
>>>
>>> -Ken
>