Kevin, From what i understand SystemVerilog approved a few weeks ago that Verilog-AMS would be a dot standard to the current P1800 standard. I dont think its going to be part of P1800 itself - atleast not at this point but an extension to it. So I dont know the exact naming conventions but it was supposed to be P1800.<number> or whatever they name it. I discussed this issue in the committee meeting last week. For this we would have to go through IEEE to create a new standards process to get this approval from IEEE. cheers, Sri Kevin Cameron wrote: > > Verilog-AMS isn't supposed to be an "external" HDL, it is supposed to be > getting integrated into SystemVerilog at some point. > > Or is there no intention to integrate it? > > Kev. > > Neil Korpusik wrote: > >> Hi all, >> >> A new technical committee (SV-XC) is being formed under P1800 >> for defining the interface between SystemVerilog 2008 and >> external hardware description languages such as: >> VHDL, V-AMS and SystemC. The chair for the committee is >> Somdipta Basu Roy, (TI Dallas) and the co-chair for the committee is >> Logie Ramachandran (Synopsys, Mountain View). >> >> The first meeting for this committee is scheduled for Wednesday >> December 6th. We would like to invite everyone interested in >> participating in this committee to our first meeting. The details >> are attached below. >> >> Thanks, >> >> Somdipta Basu Roy & Logie Ramachandran >> >> >> ------------------------------------------------------------------ >> >> SV-XC Committee Meeting >> Date: Wednesday, December 6, 2006 >> Time: 8:00am-10:00am PST >> >> Toll Free Dial In Number: (888)635-9997 >> International Access/Caller Paid Dial In Number: (763)315-6815 >> PARTICIPANT CODE: 564437 >> >> >> Agenda >> ------ >> >> 1. Review IEEE patent policy >> >> http://standards.ieee.org/board/pat/pat-slideset.ppt >> >> 2. PAR >> >> We will be operating under the latest 1800 PAR that was recently >> approved by the IEEE: >> >> http://standards.ieee.org/board/nes/projects/1800.pdf >> >> "The new revision of the standard will include resolutions and >> clarifications to Errata and critical enhancements that will >> enable successful usage of the hardware design and verification >> language. Furthermore, and as SystemVerilog is a superset of >> Verilog, the new revision will merge with Verilog 1364-2005 >> standard to ensure a single reference manual for users and >> EDA vendors alike. The new standard will also enable >> interoperability with existing languages such as VHDL >> and SystemC, as well as integration with Analog Mixed Signal (AMS)." >> >> 3. Scope of work >> >> The charter is as follows: >> >> SV-XC is responsible for defining the interface between >> SystemVerilog 2008 and external hardware description languages such as: >> VHDL, V-AMS, SystemC. In particular, simulation cycle interface, >> how do types match, naming conventions, VPI/API and so on. >> The SV-XC committee is responsible for coordinating its work with >> equivalent efforts on the part of the other languages to ensure that >> the system of languages agree on both sides of the interface. >> >> 4. Meeting frequency. >> >> Suggested frequency: twice a month, to be discussed during the Dec 6th >> meeting. >> >> 5. Issue database >> >> The existing database at http://www.eda.org/svdb will be enhanced to >> track all the issues and proposals that arise in this committee. >> >> >> 6. SV-XC alias and website >> >> An sv-xc email alias and a website will be setup for email >> discussions. >> >> >> > -- Srikanth Chandrasekaran DTO Tools Development Freescale Semiconductor Inc. Ph: +91-120-439 7021 F: x5199Received on Sun Dec 3 22:51:10 2006
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